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1
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84908388119
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Correction Feasibility Study on 3GPP system to WLAN interworking
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v6.2.0
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Third Generation Partnership Project (3GPP), "Feasibility Study on 3GPP system to WLAN interworking," 3GPP TR 22.934 v6.2.0, 2003, www.3gpp.org
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(2003)
3GPP TR 22.934
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Third Generation Partnership Project (3GPP)1
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2
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33645164978
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Wireless multi-standard terminals: System analysis and design of a reconfigurable RF front-end
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F. Agnelli, G. Albasini, I. Bietti, A. Gnudi, A. Lacaita, D. Manstretta, R. Rovatti, E. Sacchi, P. Savazzi, F. Svelto, E. Temporiti, S. Vitali, R. Castello, "Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end," in IEEE Circuits and Systems Magazine, vol. 6, no. 1, pp. 38-59, 2006
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(2006)
IEEE Circuits and Systems Magazine
, vol.6
, Issue.1
, pp. 38-59
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Agnelli, F.1
Albasini, G.2
Bietti, I.3
Gnudi, A.4
Lacaita, A.5
Manstretta, D.6
Rovatti, R.7
Sacchi, E.8
Savazzi, P.9
Svelto, F.10
Temporiti, E.11
Vitali, S.12
Castello, R.13
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3
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84892987071
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Software radios-survey, critical evaluation and future directions
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19-20 May
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J. Mitola III, "Software radios-survey, critical evaluation and future directions", National Telesystems Conference 1992, pp.13/15-13/23, 19-20 May 1992
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(1992)
National Telesystems Conference
, vol.1992
, pp. 13/15-13/23
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Mitola, J.1
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4
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0026406874
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An integrated Si bipolar RF transceiver for a zero if 900 MHz GSM digital mobile radio frontend of a hand portable phone
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12-15 May
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J. Sevenhans, A. Vanwelsenaers, J. Wenin, J. Baro, "An integrated Si bipolar RF transceiver for a zero IF 900 MHz GSM digital mobile radio frontend of a hand portable phone," Proceedings of the IEEE 1991 CICC, pp.7.7/1-7.7/4, 12-15 May 1991
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(1991)
Proceedings of the IEEE 1991 CICC
, pp. 771-774
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Sevenhans, J.1
Vanwelsenaers, A.2
Wenin, J.3
Baro, J.4
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5
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0037346005
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Second-order intermodulation mechanisms in CMOS downconverters
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Mar
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D. Manstretta, M. Brandolini, F. Svelto, "Second-order intermodulation mechanisms in CMOS downconverters," IEEE Journal of Solid-State Circuits, vol.38, no.3, pp. 394-406, Mar 2003
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(2003)
IEEE Journal of Solid-State Circuits
, vol.38
, Issue.3
, pp. 394-406
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-
Manstretta, D.1
Brandolini, M.2
Svelto, F.3
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6
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33645666620
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A 0.13μm CMOS front-end for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier
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Apr
-
A. Liscidini, M. Brandolini, D. Sanzogni, R. Castello, "A 0.13μm CMOS Front-End for DCS1800/UMTS/802.11b-g With Multiband Positive Feedback Low-Noise Amplifier," IEEE Journal of Solid- State Circuits, vol. 41, no. 4, pp. 981-989, Apr. 2006.
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(2006)
IEEE Journal of Solid- State Circuits
, vol.41
, Issue.4
, pp. 981-989
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-
Liscidini, A.1
Brandolini, M.2
Sanzogni, D.3
Castello, R.4
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7
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16244379868
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A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications
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March
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P. Rossi, A. Liscidini, M. Brandolini, F. Svelto, "A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications," IEEE Journal of Solid-State Circuits, vol. 40 , no. 3, pp. 690-697, March 2005.
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(2005)
IEEE Journal of Solid-State Circuits
, vol.40
, Issue.3
, pp. 690-697
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Rossi, P.1
Liscidini, A.2
Brandolini, M.3
Svelto, F.4
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8
-
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0242443682
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A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver
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21-24 Sept
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E. Sacchi, I. Bietti, S. Erba, L. Tee, P. Vilmercati, R. Castello, "A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver," Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, pp. 459-462, 21-24 Sept. 2003
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(2003)
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference
, pp. 459-462
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-
Sacchi, E.1
Bietti, I.2
Erba, S.3
Tee, L.4
Vilmercati, P.5
Castello, R.6
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9
-
-
39049125136
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Common Gate Trasnformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End
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to be presented at, Sept
-
A. Liscidini, C. Ghezzi, E. Depaoli, G. Albasini, I. Bietti, R. Castello, "Common Gate Trasnformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End," to be presented at IEEE 2006 Custom Integrated Circuits Conference, Sept. 2006
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(2006)
IEEE 2006 Custom Integrated Circuits Conference
-
-
Liscidini, A.1
Ghezzi, C.2
Depaoli, E.3
Albasini, G.4
Bietti, I.5
Castello, R.6
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10
-
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4444377645
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A 700- kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications
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Sept
-
E. Temporiti, G. Albasini, I. Bietti, R. Castello, M. Colombo, "A 700- kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications," IEEE Journal of Solid-State Circuits, vol.39, pp.1446-1454, Sept. 2004
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(2004)
IEEE Journal of Solid-State Circuits
, vol.39
, pp. 1446-1454
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-
Temporiti, E.1
Albasini, G.2
Bietti, I.3
Castello, R.4
Colombo, M.5
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11
-
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33645138113
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Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals
-
First Quarter
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A. Baschirotto, R. Castello, F. Campi, G. Cesura, M. Toma, R. Guerrieri, R. Lodi, L. Lavagno, P. Malcovati, "Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals," IEEE Circuits and Systems Magazine, vol.6, no.1, pp. 8-28, First Quarter 2006
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(2006)
IEEE Circuits and Systems Magazine
, vol.6
, Issue.1
, pp. 8-28
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-
Baschirotto, A.1
Castello, R.2
Campi, F.3
Cesura, G.4
Toma, M.5
Guerrieri, R.6
Lodi, R.7
Lavagno, L.8
Malcovati, P.9
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12
-
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33746401887
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A 1.2V-21dBm OIP3 4thorder active-gm-RC reconfigurable (UMTS/WLAN) filter with onchip tuning designed with an automatic tool
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12-16 Sept
-
S. D'Amico, V. Giannini, A. Baschirotto, "A 1.2V-21dBm OIP3 4thorder active-gm-RC reconfigurable (UMTS/WLAN) filter with onchip tuning designed with an automatic tool," Proceedings of the 31st ESSCIRC, pp. 315-318, 12-16 Sept. 2005
-
(2005)
Proceedings of the 31st ESSCIRC
, pp. 315-318
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-
D'Amico, S.1
Giannini, V.2
Baschirotto, A.3
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13
-
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0033893576
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Digital cancellation of D/A converter noise in pipelined A/D converters
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Mar
-
I. Galton, "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Transactions on Circuits and Systems II, vol.47, no.3, pp.185-196, Mar 2000
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(2000)
IEEE Transactions on Circuits and Systems II
, vol.47
, Issue.3
, pp. 185-196
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Galton, I.1
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14
-
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0033893202
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Gain error correction technique for pipelined analogue-to-digital converters
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30 Mar
-
E. J. Siragusa, I. Galton, "Gain error correction technique for pipelined analogue-to-digital converters," Electronics Letters , vol.36, no.7, pp.617-618, 30 Mar 2000
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(2000)
Electronics Letters
, vol.36
, Issue.7
, pp. 617-618
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Siragusa, E.J.1
Galton, I.2
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15
-
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0141954044
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Background calibration techniques for multistage pipelined ADCs with digital redundancy
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Sept
-
J. Li; U-K Moon, "Background calibration techniques for multistage pipelined ADCs with digital redundancy," IEEE Transactions on Circuits and Systems II, vol.50, no.9, pp. 531-538, Sept. 2003
-
(2003)
IEEE Transactions on Circuits and Systems II
, vol.50
, Issue.9
, pp. 531-538
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-
Li, J.1
Moon, U.-K.2
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16
-
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46749111189
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A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals
-
to be presented at, Sept
-
W. Audoglio, E. Zuffetti, G. Cesura, R. Castello, "A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals", to be presented at ESSCIRC, Sept 2006
-
(2006)
ESSCIRC
-
-
Audoglio, W.1
Zuffetti, E.2
Cesura, G.3
Castello, R.4
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17
-
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0037514615
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A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35μm CMOS
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May
-
E: Hegazi, A. A. Abidi, "A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35μm CMOS," IEEE Journal of Solid-State Circuits, vol. 38, pp. 782-792, May 2003
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(2003)
IEEE Journal of Solid-State Circuits
, vol.38
, pp. 782-792
-
-
Hegazi, E.1
Abidi, A.A.2
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18
-
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49549093759
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A multi-standard WLAN RF frontend transmitter with single-spiral dual-resonant tank loads
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to be presented at, Sept
-
G. Albasini, L. Mori, I. Bietti, "A multi-standard WLAN RF frontend transmitter with single-spiral dual-resonant tank loads", to be presented at ESSCIRC, Sept 2006
-
(2006)
ESSCIRC
-
-
Albasini, G.1
Mori, L.2
Bietti, I.3
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19
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29044446750
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A 0.83-2.5-GHz continuously tunable quadrature VCO
-
Dec
-
Guermandi, D.; Tortori, P.; Franchi, E.; Gnudi, A., "A 0.83-2.5-GHz continuously tunable quadrature VCO," IEEE Journal of Solid-State Circuits, vol.40, no.12, pp. 2620-2627, Dec. 2005
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(2005)
IEEE Journal of Solid-State Circuits
, vol.40
, Issue.12
, pp. 2620-2627
-
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Guermandi, D.1
Tortori, P.2
Franchi, E.3
Gnudi, A.4
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20
-
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0344512371
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Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
-
Nov
-
R. B. Staszewski, D. Leipold, K. Muhammad, P. T. Balsara, "Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, no.11, pp. 815-828, Nov. 2003
-
(2003)
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol.50
, Issue.11
, pp. 815-828
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-
Staszewski, R.B.1
Leipold, D.2
Muhammad, K.3
Balsara, P.T.4
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21
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84865431137
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A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter
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to be presented at, Sept
-
R. Tonietto, E. Zuffetti, I. Bietti, R. Castello, "A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter", to be presented at ESSCIRC, Sept. 2006
-
(2006)
ESSCIRC
-
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Tonietto, R.1
Zuffetti, E.2
Bietti, I.3
Castello, R.4
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