A DDS-Based PLL for 2.4-Ghz Frequency Synthesis

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 50, Issue 12, 2003, Pages 1007-1010

  Bonfanti, A ^a   Amorosa, F ^a,b   Samori, C ^a   Lacaita, A L ^a  

^a POLITECNICO DI MILANO   (Italy)

^b Accent   (Italy)

Author keywords

Direct digital synthesizer (DDS); Frequency synthesis; Phase noise; Phase locked loop (PLL); Wireless communication

Indexed keywords

BANDWIDTH; CALIBRATION; CORRELATION METHODS; FREQUENCY DIVIDING CIRCUITS; FREQUENCY MODULATION; FREQUENCY SYNTHESIZERS; LINEAR SYSTEMS; MATHEMATICAL MODELS; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE; TUNING;

DIRECT DIGITAL SYNTHESIZER (DDS); FRACTIONAL DIVIDERS; FREQUENCY SYNTHESIS; PHASE NOISE; WIRELESS COMMUNICATION;

PHASE LOCKED LOOPS;

EID: 0346076816     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.820250     Document Type: Article

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