Mixed hierarchical-functional fault models for targeting sequential cores

Journal of Systems Architecture

Volumn 54, Issue 3-4, 2008, Pages 465-477

  Raik, Jaan ^a   Ubar, Raimund ^a   Viilukas, Taavi ^a   Jenihhin, Maksim ^a  

^a TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

Automated test pattern generation; Decision diagrams; Functional fault models; Sequential circuits

Indexed keywords

DECISION TREES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIPLEXING; PATTERN RECOGNITION; SEQUENTIAL CIRCUITS;

AUTOMATED TEST PATTERN GENERATION; FUNCTIONAL BLOCKS; FUNCTIONAL FAULT MODELS; PATTERN GENERATION TOOLS;

HIERARCHICAL SYSTEMS;

EID: 42949134907     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2007.07.003     Document Type: Article

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