Sequential circuit test generation using dynamic state traversal

Proceedings of the 1997 European Conference on Design and Test, EDTC 1997

Volumn , Issue , 1997, Pages 23-28

  Hsiao, Michael S ^a   Rudnick, Elizabeth M ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GENETIC ALGORITHMS; GENETIC ENGINEERING; SEQUENTIAL CIRCUITS; TIMING CIRCUITS;

FAULT COVERAGES; SEQUENTIAL CIRCUIT TEST GENERATION; STATE TRANSFER; TARGET FAULTS; TARGET STATE; TEST VECTORS; 'CURRENT; DETERMINISTICS;

TESTING; GENETIC ALGORITHMS;

EID: 85029662692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/edtc.1997.582325     Document Type: Conference Paper

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