Fast test pattern generation for sequential circuits using decision diagram representations

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 3, 2000, Pages 213-226

  Raik, Jaan ^a   Ubar, Raimund ^a,b  

^a TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

^b BAUMAN MOSCOW STATE TECHNICAL UNIVERSITY   (Russian Federation)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONSTRAINT THEORY; DECISION THEORY; PROBLEM SOLVING; SEQUENTIAL CIRCUITS;

DECISION DIAGRAM REPRESENTATIONS; FAST TEST PATTERN GENERATION; REGISTER TRANSFER LEVEL;

INTEGRATED CIRCUIT TESTING;

EID: 0033719467     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008335130158     Document Type: Article

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