Delay-insensitive, point-to-point interconnect using M-of-N codes

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2003, Pages 132-140

  Bainbridge, W J ^a   Toms, W B ^a   Edwards, D A ^a   Furber, S B ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DELAY CIRCUITS; ENCODING (SYMBOLS); INTEGRATED CIRCUIT INTERCONNECTS; NETWORK-ON-CHIP; SIGNAL ENCODING;

BINARY DATA; COST EFFECTIVE; ENCODING/DECODING; NETWORK-ON-CHIP DESIGN; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; SELF-TIMED; SIMPLE++;

MAPPING;

EID: 77957960152     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2003.1199173     Document Type: Conference Paper

References (13)

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