Speculative decoupled software pipelining

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2007, Pages 49-59

  Vachharajani, Neil ^a   Rangan, Ram ^a,b   Raman, Easwaran ^a   Bridges, Matthew J ^a   Ottoni, Guilherme ^a   August, David I ^a  

^a Princeton University   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); JOINTS (STRUCTURAL COMPONENTS); PARALLEL PROCESSING SYSTEMS; PIPELINES; PROGRAM COMPILERS; TURBO CODES;

CHIP MULTI PROCESSOR; COMPILATION TECHNIQUES; COMPILER IMPLEMENTATION; EXECUTION EFFICIENCY; INTER-CORE COMMUNICATION; INTERNATIONAL CONFERENCES; MULTI-CORE PROCESSORS; MULTIPLE THREADS; PARALLEL ARCHITECTURES; PARALLELIZING; PIPELINE ORGANIZATION; PROCESSOR MODELING; SOFTWARE PIPELINING; VARIETY OF CODES;

MICROPROCESSOR CHIPS;

EID: 41349089872     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2007.34     Document Type: Conference Paper

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