Design of VLSI implementation-oriented LDPC codes

IEEE Vehicular Technology Conference

Volumn 58, Issue 1, 2003, Pages 670-673

  Zhong, Hao ^a   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; DECODING; MATRIX ALGEBRA; SIGNAL TO NOISE RATIO; VLSI CIRCUITS; FORWARD ERROR CORRECTION; INTEGRATED CIRCUIT DESIGN; SATELLITE COMMUNICATION SYSTEMS;

DECODERS; ERROR-CORRECTING PERFORMANCE; LOW-DENSITY PARITY-CHECK (LDPC) CODES; PARITY CHECK MATRIX;

CODES (SYMBOLS);

CONTROL MECHANISM; DECODER IMPLEMENTATION; ERROR-CORRECTING; LOW-DENSITY PARITY-CHECK (LDPC) CODES; PARTIALLY-PARALLEL DECODER; REAL APPLICATIONS; REGULAR STRUCTURE; VLSI IMPLEMENTATION;

EID: 4143136413     PISSN: 07400551     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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