Parallel decoding architectures for low density parity check codes

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 742-745

  Howland, C ^a   Blanksby, A ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODING GAINS; DESIGN AND IMPLEMENTATIONS; HIGH THROUGHPUT; LOW-DENSITY PARITY-CHECK (LDPC) CODES; LOW-POWER DISSIPATION; PARALLEL DECODING; PARALLEL LDPC DECODERS; SOFT DECISION;

PARALLEL ARCHITECTURES;

DECODING;

EID: 84888029103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922344     Document Type: Conference Paper

References (11)

1. M. Bossert, Channel Coding for Telecommunications, John Wiley & Sons, 1999.
2. C. Berrou, A. Glavieux and P. Thitimajshima, "Near Shannon limit error-correcting codes and decoding", Proc. Int. Conf. Comm. '93, pp 1064-1070, May 1993.
3. R. Pyndiah, A. Glavieux, A. Picart, and S. Jacq, "Near optimum decoding of product codes", Proc. IEEE GLOBECOM '94, pp 339-343. 1994.
4. R. Gallager. "Low density parity check codes", IRE Trans. Info. Theory, Vol. IT-8, pp 21-28, Jan. 1962.
5. D. MacKay and R. Neal, "Near Shannon limit performance of low density parity check codes", Electron. Lett. Vol. 32(18), pp 1645-1646, Aug. 1996.
6. T. Richardson, A. Shokrollahi, and R. Urbanke, "Design of provably good low-density parity check codes", submitted to IEEE Trans. Inf. Theoiy, March 1999.
7. S. Hong and W. Stark, "Design and implementation of a low complexity VLSI turbo-code decoder architecture for low energy mobile wireless communications", J. VLSI Sig. Proc, Vol. 24, pp 43-57, 2000.
8. L.R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate", IEEE Trans on Inf. Theory, pp 363-77, March 1974.
9. F.R. Kschischang and B.J. Frey, "Iterative Decoding of Compound Codes by Probability Propagation in Graphical Models", IEEE Journal on Selected Areas in Communications, Vol. 16. No. 2, pp 219-30, Feb. 2000.
10. P.J. Black and T. H. Y. Meng, "A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder", IEEE Journal of Solid State Circuits, Vol. 32 No. 6, pp 797-805, June 1997.
11. "3ld Generation Partnership Project (3GPP); Technical Specification Group Radio Access Network Multiplexing and channel coding (TDD)", available at http://www.3qpp.orq