-
1
-
-
33746799544
-
Ultrathin strained-SOI by stress balance on compliant substrates and FET performance
-
Oct
-
Y. Haizhou, K. D. Hobart, R. L. Peterson, F. J. Kub, and J. C. Sturm, "Ultrathin strained-SOI by stress balance on compliant substrates and FET performance," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2207-2214, Oct. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.10
, pp. 2207-2214
-
-
Haizhou, Y.1
Hobart, K.D.2
Peterson, R.L.3
Kub, F.J.4
Sturm, J.C.5
-
2
-
-
11144354892
-
A logic nanotechnology featuring strained-silicon
-
Apr
-
S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, M. Zhiyong, B. McIntyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, no. 4, pp. 191-193, Apr. 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.4
, pp. 191-193
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Cea, S.4
Chau, R.5
Glass, G.6
Hoffman, T.7
Klaus, J.8
Zhiyong, M.9
McIntyre, B.10
Murthy, A.11
Obradovic, B.12
Shifren, L.13
Sivakumar, S.14
Tyagi, S.15
Ghani, T.16
Mistry, K.17
Bohr, M.18
El-Mansy, Y.19
-
3
-
-
33847754669
-
Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations
-
A. V. Y. Thean, L. Prabhu, V. Vartanian, M. Ramon, B. Y. Nguyen, T. White, H. Collard, Q. H. Xie, S. Murphy, J. Cheek, S. Venkatesan, J. Mogab, C. H. Chang, Y. H. Chiu, H. C. Tuan, Y. C. See, M. S. Liang, and Y. C. Sun, "Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations," in IEEE IEDM Tech. Dig. 2005, pp. 509-512.
-
(2005)
IEEE IEDM Tech. Dig
, pp. 509-512
-
-
Thean, A.V.Y.1
Prabhu, L.2
Vartanian, V.3
Ramon, M.4
Nguyen, B.Y.5
White, T.6
Collard, H.7
Xie, Q.H.8
Murphy, S.9
Cheek, J.10
Venkatesan, S.11
Mogab, J.12
Chang, C.H.13
Chiu, Y.H.14
Tuan, H.C.15
See, Y.C.16
Liang, M.S.17
Sun, Y.C.18
-
4
-
-
33847287986
-
-
M. Horstmann, A. Wei, T. Kammler, J. Hntschel, H. Bierstedt, T. Feudel, K. Frohberg, M. Gerhardt, A. Hellmich, K. Hempel, J. Hohage, P. Javorka, J. Klais, G. Koerner, M. Lenski, A. Neu, R. Otterbach, P. Press, C. Reichel, M. Trentsch, B. Trui, H. Salz, M. Schaller, H. J. Engelmann, O. Herzog, H. Ruelke, P. Hubler, R. Stephan, D. Greenlaw, M. Raab, and N. Kepler, Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies, in IEEE IEDM Tech. Dig. 2005, pp. 233-236.
-
M. Horstmann, A. Wei, T. Kammler, J. Hntschel, H. Bierstedt, T. Feudel, K. Frohberg, M. Gerhardt, A. Hellmich, K. Hempel, J. Hohage, P. Javorka, J. Klais, G. Koerner, M. Lenski, A. Neu, R. Otterbach, P. Press, C. Reichel, M. Trentsch, B. Trui, H. Salz, M. Schaller, H. J. Engelmann, O. Herzog, H. Ruelke, P. Hubler, R. Stephan, D. Greenlaw, M. Raab, and N. Kepler, "Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies," in IEEE IEDM Tech. Dig. 2005, pp. 233-236.
-
-
-
-
5
-
-
0028383440
-
Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors
-
J. Welser, J. L. Hoyt, and J. F. Gibbons, "Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors," IEEE Electron Device Lett., vol. 15, pp. 100-102, 1994.
-
(1994)
IEEE Electron Device Lett
, vol.15
, pp. 100-102
-
-
Welser, J.1
Hoyt, J.L.2
Gibbons, J.F.3
-
6
-
-
4544268942
-
MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node
-
S. Pidin, T. Mori, R. Nakamura, T. Saiki, R. Tanabe, S. Satoh, M. Kase, K. Hashimoto, and T. Sugii, "MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node," in VLSI Symp. Tech. Dig. 2004, pp. 54-55.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 54-55
-
-
Pidin, S.1
Mori, T.2
Nakamura, R.3
Saiki, T.4
Tanabe, R.5
Satoh, S.6
Kase, M.7
Hashimoto, K.8
Sugii, T.9
-
7
-
-
33846276277
-
-
A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokuma, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, I. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima, and F. Matsuoka, High performance CMOSFET technology for 45 nm generation and scalability of stress-induced mobility enhancement technique, in IEEE IEDM Tech. Dig. 2005, pp. 229-232.
-
A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokuma, K. Eda, T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo, H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku, T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa, K. Saki, S. Mori, K. Ohno, I. Mizushima, M. Saito, M. Iwai, S. Yamada, N. Nagashima, and F. Matsuoka, "High performance CMOSFET technology for 45 nm generation and scalability of stress-induced mobility enhancement technique," in IEEE IEDM Tech. Dig. 2005, pp. 229-232.
-
-
-
-
8
-
-
41149093057
-
-
K. Ota, T. Sanuki, K. Yahashi, Y. Miyanami, K. Matsuo, J. Idebuchi, M. Moriya, K. Nakayama, R. Yamaguchi, H. Tanaka, T. Yamazaki, S. Terauchi, A. Horiuchi, S. Fujita, I. Mizushima, H. Yamasaki, K. Nagaoka, A. Oishi, Y. Takegawa, K. Ohno, and M. Iwai and Saito, Scalable eSiGe S/D technology with less layout dependence for 45-nm generation, in VLSI Symp. Tech. Dig. 2006, pp. 64-65.
-
K. Ota, T. Sanuki, K. Yahashi, Y. Miyanami, K. Matsuo, J. Idebuchi, M. Moriya, K. Nakayama, R. Yamaguchi, H. Tanaka, T. Yamazaki, S. Terauchi, A. Horiuchi, S. Fujita, I. Mizushima, H. Yamasaki, K. Nagaoka, A. Oishi, Y. Takegawa, K. Ohno, and M. Iwai and Saito, "Scalable eSiGe S/D technology with less layout dependence for 45-nm generation," in VLSI Symp. Tech. Dig. 2006, pp. 64-65.
-
-
-
-
9
-
-
0036923437
-
Novel locally strained channel technique for high performance 55 ran CMOS
-
K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto, and Y. Inoue, "Novel locally strained channel technique for high performance 55 ran CMOS," in IEDM Tech. Dig. 2002, pp. 27-30.
-
(2002)
IEDM Tech. Dig
, pp. 27-30
-
-
Ota, K.1
Sugihara, K.2
Sayama, H.3
Uchida, T.4
Oda, H.5
Eimori, T.6
Morimoto, H.7
Inoue, Y.8
-
10
-
-
17744399086
-
Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride
-
Apr
-
L. Tsung Yi and C. Tien Sheng, "Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride," IEEE Electron Device Lett., vol. 26, no. 4, pp. 267-269, Apr. 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.4
, pp. 267-269
-
-
Tsung Yi, L.1
Tien Sheng, C.2
-
11
-
-
33845877965
-
Phenomenological model for "stress memorization" effect from a capped-poly process
-
L. S. Adam, C. Chiu, M. Huang, X. Wang, Y. Wang, S. Singh, Y. Chen, H. Bu, and J. Wu, "Phenomenological model for "stress memorization" effect from a capped-poly process," in Simul. Semicond. Process. Devices Int. Conf. (SISPAD 2005), pp. 139-142.
-
Simul. Semicond. Process. Devices Int. Conf. (SISPAD 2005)
, pp. 139-142
-
-
Adam, L.S.1
Chiu, C.2
Huang, M.3
Wang, X.4
Wang, Y.5
Singh, S.6
Chen, Y.7
Bu, H.8
Wu, J.9
-
12
-
-
46049090047
-
Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure
-
R. A. Donaton, D. Chidambarrao, J. Johnson, P. Chang, Y. Liu, W. K. Henson, J. Holt, X. Li, J. Li, A. Domenicucci, A. Madan, K. Rim, and C. Wann, "Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure," in IEEE IEDM Tech. Dig. 2006, pp. 465-468.
-
(2006)
IEEE IEDM Tech. Dig
, pp. 465-468
-
-
Donaton, R.A.1
Chidambarrao, D.2
Johnson, J.3
Chang, P.4
Liu, Y.5
Henson, W.K.6
Holt, J.7
Li, X.8
Li, J.9
Domenicucci, A.10
Madan, A.11
Rim, K.12
Wann, C.13
-
13
-
-
39749173824
-
Beneath-the-channel strain-transfer-structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs
-
Papers, pp
-
K.-W. Ang, J. Lin, C.-H. Tung, N. Balasubramanian, G. S. Samudra, and Y. -C. Yeo, "Beneath-the-channel strain-transfer-structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs," 2007 VLSI Symp. Tech. Dig. Tech. Papers, pp. 42-43.
-
(2007)
VLSI Symp. Tech. Dig. Tech
, pp. 42-43
-
-
Ang, K.-W.1
Lin, J.2
Tung, C.-H.3
Balasubramanian, N.4
Samudra, G.S.5
Yeo, Y.-C.6
-
14
-
-
34447290233
-
Strained n-channel transistors with silicon source and drain regions and embedded silicon/germanium as strain-transfer structure
-
K.-W. Ang, C.-H. Tung, N. Balasubramanian, G. S. Samudra, and Y.-C. Yeo, "Strained n-channel transistors with silicon source and drain regions and embedded silicon/germanium as strain-transfer structure," Electron Device Lett., IEEE, vol. 28, pp. 609-612, 2007.
-
(2007)
Electron Device Lett., IEEE
, vol.28
, pp. 609-612
-
-
Ang, K.-W.1
Tung, C.-H.2
Balasubramanian, N.3
Samudra, G.S.4
Yeo, Y.-C.5
-
15
-
-
39749102335
-
-
Online. Available
-
"ITRS 2005 Edition Online. Available: http://www.itrs.net/Links/ 20051TRS/Home2005.htm."
-
(2005)
Edition
-
-
-
16
-
-
25644458690
-
Molecular dynamics study on size-dependent elastic properties of silicon nanocantilevers
-
S. H. Park, J. S. Kim, J. S. Lee, Y. K. Choi, and O. M. Kwon, "Molecular dynamics study on size-dependent elastic properties of silicon nanocantilevers," in Thin Solid Films, 2005, vol. 492, pp. 285-289.
-
(2005)
Thin Solid Films
, vol.492
, pp. 285-289
-
-
Park, S.H.1
Kim, J.S.2
Lee, J.S.3
Choi, Y.K.4
Kwon, O.M.5
-
17
-
-
33745131438
-
Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS
-
D. Chanemougame, S. Monfray, F. Boeuf, A. Talbot, N. Loubet, F. Payet, V. Fiori, S. Orain, F. Leverd, D. Delille, B. Duriez, A. Souifi, D. Dutartre, and T. Skotnicki, "Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS," in VLSI Symp. Tech. Dig. 2005, pp. 180-181.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 180-181
-
-
Chanemougame, D.1
Monfray, S.2
Boeuf, F.3
Talbot, A.4
Loubet, N.5
Payet, F.6
Fiori, V.7
Orain, S.8
Leverd, F.9
Delille, D.10
Duriez, B.11
Souifi, A.12
Dutartre, D.13
Skotnicki, T.14
-
18
-
-
33847697736
-
Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime
-
K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, "Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime," in IEEE IEDM Tech. Dig. 2005, pp. 129-132.
-
(2005)
IEEE IEDM Tech. Dig
, pp. 129-132
-
-
Uchida, K.1
Krishnamohan, T.2
Saraswat, K.C.3
Nishi, Y.4
-
19
-
-
0036927652
-
Strained-silicon MOSFET technology
-
J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, "Strained-silicon MOSFET technology," in IEDM Tech. Dig. 2002, pp. 23-26.
-
(2002)
IEDM Tech. Dig
, pp. 23-26
-
-
Hoyt, J.L.1
Nayfeh, H.M.2
Eguchi, S.3
Aberg, I.4
Xia, G.5
Drake, T.6
Fitzgerald, E.A.7
Antoniadis, D.A.8
-
20
-
-
0043175310
-
Scalability of strained-Si nMOSFETs down to 25 nm gate length
-
J.-S. Goo, Q. Xiang, Y. Takamura, W. Haihong, J. Pan, F. Arasnia, E. N. Paton, P. Besser, M. V. Sidorov, E. Adem, A. Lochtefeld, G. Braithwaite, M. T. Currie, R. Hammond, M. T. Bulsara, and L. Ming-Ren, "Scalability of strained-Si nMOSFETs down to 25 nm gate length," IEEE Electron Device Lett., vol. 24, pp. 351-353, 2003.
-
(2003)
IEEE Electron Device Lett
, vol.24
, pp. 351-353
-
-
Goo, J.-S.1
Xiang, Q.2
Takamura, Y.3
Haihong, W.4
Pan, J.5
Arasnia, F.6
Paton, E.N.7
Besser, P.8
Sidorov, M.V.9
Adem, E.10
Lochtefeld, A.11
Braithwaite, G.12
Currie, M.T.13
Hammond, R.14
Bulsara, M.T.15
Ming-Ren, L.16
-
21
-
-
0347758355
-
Film thickness constraints for manufacturable strained-silicon CMOS
-
J. G. Fiorenza, G. Braithwaite, C. W. Leitz, M. T. Currie, J. Yap, F. Singaporewala, V. K. Yang, T. A. Langdo, J. Carlin, M. Somerville, A. Lochtefeld, H. Badawi, and M. T. Bulsara, "Film thickness constraints for manufacturable strained-silicon CMOS," Semicond. Sci. Technol. vol. 19, pp. 4-8, 2004.
-
(2004)
Semicond. Sci. Technol
, vol.19
, pp. 4-8
-
-
Fiorenza, J.G.1
Braithwaite, G.2
Leitz, C.W.3
Currie, M.T.4
Yap, J.5
Singaporewala, F.6
Yang, V.K.7
Langdo, T.A.8
Carlin, J.9
Somerville, M.10
Lochtefeld, A.11
Badawi, H.12
Bulsara, M.T.13
-
22
-
-
0346955939
-
Defects in epitaxial multilayers: I. Misfit dislocations
-
J. W. Matthews and A. E. Blakeslee, "Defects in epitaxial multilayers: I. Misfit dislocations," J. Cryst. Growth, vol. 27, pp. 118-125, 1974.
-
(1974)
J. Cryst. Growth
, vol.27
, pp. 118-125
-
-
Matthews, J.W.1
Blakeslee, A.E.2
-
23
-
-
84956263829
-
GexSil-x/Si strained-layer superlattice grown by molecular beam epitaxy
-
Oct. 3-Nov. 4
-
J. C. Bean, L. C. Feldman, A. T. Fiory, S. Nakahara, and I. K. Robinson, "GexSil-x/Si strained-layer superlattice grown by molecular beam epitaxy," in Proc. 30th Natl. Symp. Amer. Vacuum. Soc., Oct. 3-Nov. 4, 1983, pp. 436-440.
-
(1983)
Proc. 30th Natl. Symp. Amer. Vacuum. Soc
, pp. 436-440
-
-
Bean, J.C.1
Feldman, L.C.2
Fiory, A.T.3
Nakahara, S.4
Robinson, I.K.5
-
24
-
-
0029276715
-
-
D. L. Harame, J. H. Comfort, J. D. Cressler, E. F. Crabbe, J. Y. C. Sun, B. S. Meyerson, and T. Tice, Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits, IEEE Trans. Electron Devices, 42, pp. 455-468, 1995.
-
D. L. Harame, J. H. Comfort, J. D. Cressler, E. F. Crabbe, J. Y. C. Sun, B. S. Meyerson, and T. Tice, "Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits," IEEE Trans. Electron Devices, vol. 42, pp. 455-468, 1995.
-
-
-
|