Performance boost of scaled Si PMOS through Novel SiGe Stressor for HP CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 180-181

  Chanemougame, D ^a   Monfray, S ^a   Boeuf, F ^a   Talbot, A ^a   Loubet, N ^a   Payet, F ^a   Fiori, V ^a   Orain, S ^b   Leverd, F ^a   Delille, D ^b   Duriez, B ^b   Souifi, A ^c   Dutartre, D ^a   Skotnicki, T ^a  

^a STMICROELECTRONICS   (France)

^b INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

^c NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; SEMICONDUCTING SILICON COMPOUNDS; SILICON; STRESSES; TRANSISTORS;

PMOS TRANSISTOR ARCHITECTURE; SHALLOW TRENCH ISOLATION (STI); SI PMOS; SIGE STRESSORS;

MOS DEVICES;

EID: 33745131438     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469259     Document Type: Conference Paper

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