A digital BIST methodology for spread spectrum clock generators

Proceedings of the Asian Test Symposium

Volumn 2006, Issue , 2006, Pages 251-254

  Chou, Maohsuan ^a   Hsu, Jenchien ^a   Su, Chauchin ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CLOCKS; LOGIC DESIGN; PHASE METERS; TIMING JITTER;

CLOCK GENERATORS; FREQUENCY VARIATION; MULTI-PHASE PHASE DETECTORS;

BUILT-IN SELF TEST;

EID: 33947627637     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2006.261028     Document Type: Conference Paper

References (3)

1. Serial ATA Workgroup "SATA: High speed Serialized AT Attachment", Revision 1.0, 26 May 2004.
2. H.R. Lee, O. Kim, G. Ahn, and D.K. Jeong "A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 1.18μm CMOS", IEEE ISSCC, vol. 1, Feb. 2005.
3. W.T. Chen, J.C. Hsu, H.W. Lune, and C.C. Su "A spread spectrum clock generator for SATA-II", IEEE ISCAS, vol. 3, pp. 2643-2646, May 2005