An on-chip jitter measurement circuit for the PLL

Proceedings of the Asian Test Symposium

Volumn 2003-January, Issue , 2003, Pages 332-335

  Tsai, Chin Cheng ^a   Lee, Chung Len ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

JITTER; RECONFIGURABLE HARDWARE;

JITTER MEASUREMENTS; ON CHIP PLL; ON-CHIP JITTER MEASUREMENT CIRCUITS; PROCESS VARIATION; SELF CALIBRATION; VERNIER DELAY LINE;

TIMING CIRCUITS;

EID: 14944356891     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250832     Document Type: Conference Paper

References (7)

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2. Wajih Dalal & Daniel Rosenthal, "Measuring Jitter of High Speed Data Channels Using Under-sampling Techniques," Proceedings IEEE International Test Conference, 1998, pp. 814-818.
3. Stephen Sunter & Aubin Roy, "BIST for Phase-Locked Loops in Digital Applications," Proceedings IEEE International Test Conference, 1999, pp. 532-540.
4. Nazmy Abaskharoun, Mohamed Hafed & Gordon W. Roberts, "Circuits for On-Chip Sub-Nanosecond Signal Capture and Timing Measurements," Circuits and Systems, 2001, ISCAS pp. 174-177.
5. Antonio H. Chan & Gordon W. Roberts, "A Synthesizable, Fast and High-Resolution Timing Measurement Device Using A Component-Invariant Vernier Delay Line," Proceedings IEEE International Test Conference, 2001, pp. 858-867.
6. Piotr Dudek, Stanislaw Szxzepanski & John V. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line," IEEE Transactions on Solid-State Circuits, Vol. 35, 2000, pp. 240-247.
7. Payam Heydari and Massoud Pedram, "Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective," Computer Design, 2001, pp. 209-213.