A deep sub-micron timing measurement circuit using a single-stage vernier delay line

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 77-80

  Chan, Antonio H ^a   Roberts, Gordon W ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EDGE DETECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; PROBABILITY DENSITY FUNCTION; TIMING JITTER;

JITTER MEASUREMENT; MIXED-SIGNAL CIRCUITS;

DELAY CIRCUITS;

EID: 0036045278     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A high-resolution CMOS time-to-digital converter utilizing a vernier delay line
2. BIST for phase-locked loops in digital applications
3. Circuits for on-chip subnanosecond signal capture and characterization
4. Testing and characterizing jitter in 100BASE-TX and 155.52 Mbit/s ATM devices with a 1 Gsamples/s AWG in an ATE system
5. Analysis of metastability operations in D-latches