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Volumn 2003-January, Issue , 2003, Pages 336-339

A low-cost jitter measurement technique for BIST applications

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTION FUNCTIONS; SPICE;

EID: 17644390511     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250833     Document Type: Conference Paper
Times cited : (18)

References (9)
  • 1
    • 0035684160 scopus 로고    scopus 로고
    • A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line
    • A. H. Chan and G. W. Roberts. A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line. In International Test Conference, pages 858-867, 2001.
    • (2001) International Test Conference , pp. 858-867
    • Chan, A.H.1    Roberts, G.W.2
  • 2
    • 0035687180 scopus 로고    scopus 로고
    • A high-resolution jitter measurement technique using ADC sampling
    • S. Cherubal and A. Chatterjee. A high-resolution jitter measurement technique using ADC sampling. In International Test Conference, pages 838-847, 2001.
    • (2001) International Test Conference , pp. 838-847
    • Cherubal, S.1    Chatterjee, A.2
  • 3
    • 17144435893 scopus 로고    scopus 로고
    • A high-resolution CMOS time-to-digital converter utilizing a vernier delay line
    • February
    • P. Dudek, S. Szczepanski, and J. V. Hatfield. A high-resolution CMOS time-to-digital converter utilizing a vernier delay line. IEEE Transactions on Solid-State Circuits, 35(2):240-247, February 2000.
    • (2000) IEEE Transactions on Solid-State Circuits , vol.35 , Issue.2 , pp. 240-247
    • Dudek, P.1    Szczepanski, S.2    Hatfield, J.V.3
  • 5
    • 0033315398 scopus 로고    scopus 로고
    • BIST for phase-locked loops in digital applications
    • S. Sunter and A. Roy. BIST for phase-locked loops in digital applications. In International Test Conference, pages 532-540, 1999.
    • (1999) International Test Conference , pp. 532-540
    • Sunter, S.1    Roy, A.2
  • 6
    • 0036575437 scopus 로고    scopus 로고
    • Embedded timing analysis: A SoC infrastrcture
    • May-June
    • S. Tabatabaei and A. Ivanov. Embedded timing analysis: A SoC infrastrcture. IEEE Design & Test of Computers, 19(3):22-34, May-June 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , Issue.3 , pp. 22-34
    • Tabatabaei, S.1    Ivanov, A.2
  • 9
    • 0034994760 scopus 로고    scopus 로고
    • A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals
    • T. J. Yamaguchi, M. Soma, D. Halter, R. Raina, J. Nissen, and M. Ishida. A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals. In VLSI Test Symposium, pages 102-110, 2001.
    • (2001) VLSI Test Symposium , pp. 102-110
    • Yamaguchi, T.J.1    Soma, M.2    Halter, D.3    Raina, R.4    Nissen, J.5    Ishida, M.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.