BIST for clock jitter measurements

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Cheng, Kuo Hsing ^a   Jiang, Shu Yu ^a   Chen, Zong Shen ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; SPURIOUS SIGNAL NOISE;

CLOCK JITTERS;

JITTER;

EID: 0038757969     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Bozena Kaminska, "BIST Means More Measurement Options for Designers" http://www.fluence.com/news.html.
2. Arnold M. Frisch and Thomas H. Rinderknecht, "Jitter Measurement System and Method". US Patent 6,295,315.
3. Tabatabaei S. Ivanov A., "Embedded Timing Analysis: A SoC Infrastructure" IEEE Design and Test of Computers, May-June 2002, pages 22-34.
4. Stephen S. and Audin R., "BIST for Phase-Locked Loops in Digital Applications" Proceedings of International Test Conference, Sep 1999, pages 532-540.
5. Chan A. H. and Roberts G.W., "A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line" Proceedings of International Test Conference, Baltimore, MD, USA, Nov 2001, pages 858-867.