On-chip calibration technique for delay line based BIST jitter measurement

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Nelson, Bryan ^a   Soma, Mani ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SIGNAL FREQUENCIES; PULSE WIDTH MODULATION (PWM); TIME TO DIGITAL CONVERTERS (TDC); VERNIER DELAY LINES (VDL);

BUILT-IN SELF TEST; CALIBRATION; DELAY CIRCUITS; ELECTRIC CLOCKS; FREQUENCIES; JITTER; MICROPROCESSOR CHIPS; TUNING;

ELECTRIC CONVERTERS;

EID: 4344596820     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. A. Dancy, A. Chandrakasan, "A Reconfigurable Dual Output Low Power Digital PWM Power Converter," IEEE Transactions on Very Large Scale Integration VLSI Systems, Vol. 8, No. 3, pp. 252-263, June 2000.
3. A. H. Chan, G. W. Roberts, "A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line," Proceedings of International Test Conference, Baltimore, MD, pp. 858-867, November 2001.
4. A. H. Chan, G. W. Roberts, "A Deep Sub-Micron Timing Measurement Circuit Using a Single-Stage Vernier Delay Line," IEEE Custom Integrated Circuits Conference, Proceeding of the IEEE 2002 12-15, pp. 77-80, May 2002.
5. H. Hu, Y. Li, "A New On-chip DC-DC Voltage Down Converter For Low-Power VLSI Chip," 4th International ASIC Conference Proceedings, pp. 244-247, October 2001.
6. A. S. Sedra, K. C. Smith, Microelectronic circuits, Oxford University press, New York, 1998.
7. K. Cheng, S. Jiang, Z. Chen, "BIST for Clock Jitter Measurements," Proceedings of the 2003 International Symposium on Circuits and Systems, Volume: 5, pp. 25-28, May 2003.