High accuracy jitter measurement using cyclic pulse width modulation structure

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)

Volumn 2005, Issue , 2005, Pages 24-27

  Cheng, Kuo Hsing ^a   Jiang, Shu Yu ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CIRCUIT THEORY; CLOCKS; CYCLIC LOADS; JITTER; SIGNAL PROCESSING;

HIGH-SPEED CIRCUIT TESTING; SELECTABLE RESOLUTION; TIMING RESOLUTION; TSMC 0.25UM CMOS PROCESS;

PULSE WIDTH MODULATION;

EID: 33745435424     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2005.1500010     Document Type: Conference Paper

References (9)

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