Compatibility of Dual Metal Gate Electrodes with High-K Dielectrics for CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 323-326

  Lee, JaeHoon ^a   Suh, You Seok ^a   Lazar, Heather ^a   Jha, Rashmi ^a   Gurganus, Jason ^a   Lin, Yanxia ^a   Misra, Veena ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DIELECTRIC MATERIALS; ELECTRODES; FABRICATION; FERMI LEVEL; GATES (TRANSISTOR); MOS CAPACITORS; POLYSILICON; RUTHENIUM ALLOYS; TANTALUM COMPOUNDS; THERMODYNAMIC STABILITY;

DUAL METAL GATE ELECTRODES; EQUIVALENT OXIDE THICKNESS (EOT);

CMOS INTEGRATED CIRCUITS;

EID: 0842266647     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. C. Hobbs, et al., "Fermi Level Pinning at the PolySi/Metal Oxide Interface" IEEE Symp. on VLSI Technology Tech. Dig., 2-1.2003.
2. I. De, et. al., Impact of gate workfunction on device performance at the 50 nm technology node", Solid-State-Electronics, vol. 44, no. 6; p. 1077-80, 2000.
3. H. Zhong et al "Properties of Ru-Ta Alloys as Gate Electrodes For NMOS and PMOS Silicon Devices" IEDM Tech. Dig. p. 467, 2001.
4. y Gate Electrodes for Dual Gate Si-CMOS Devices," IEEE Symp. on VLSI Technology Tech. Dig. p. 47, 2001.
5. J. R. Hauser et al., "Characterization of ultrathin oxides using electrical C-V and I-V measurements," Characterization and Metrology for ULSI Technology, AIP Conf. Proc., p. 449, 1998.