Fermi pinning-induced thermal instability of metal-gate work functions

IEEE Electron Device Letters

Volumn 25, Issue 5, 2004, Pages 337-339

  Yu, H Y ^a   Ren, Chi ^a   Yeo, Yee Chia ^a   Kang, J F ^a,b   Wang, X P ^a   Ma, H H H ^a   Li, Ming Fu ^a,c   Chan, D S H ^a   Kwong, D L ^d  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b PEKING UNIVERSITY   (China)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

^d The University of Texas at Austin   (United States)

Author keywords

Extrinsic states; Fermi pinning; Metal gate; Thermal stability; Work function

Indexed keywords

ANNEALING; FERMI LEVEL; GATES (TRANSISTOR); INTERFACES (MATERIALS); THERMAL EFFECTS; THERMODYNAMIC STABILITY;

EXTRINSIC STATE; FERMI PINNING; METAL GATE; THERMAL INSTABILITY;

MOSFET DEVICES;

EID: 2442507891     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.827643     Document Type: Letter

References (14)

1. International Technology Roadmap for Semiconductors, (2002 Update), SIA, 2002.
2. Y.-C. Yeo, P. Ranade, T.-J. King, and C. Hu, "Effects of high-κ gate-dielectric materials on metal and silicon gate workfunctions," IEEE Electron Device Lett., vol. 23, pp. 342-344, June 2002.
3. Y.-C. Yeo, T.-J. King, and C. Hu, "metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology," J. Appl. Phys., vol. 92, pp. 7266-7271, 2002.
4. J. Westlinder, T. Schram, L. Pantisano, E. Cartier, A. Kerber, G. S. Lujan, J. Olsson, and G. Groeseneken, "On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices," IEEE Electron Device Lett., vol. 24, pp. 550-552, Sept. 2003.
5. J. Lee, H. Zhong, Y. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra, "Tunable work function dual metal gate technology for bulk and nonbulk CMOS," in IEDM Tech. Dig., 2002, pp. 359-362.
6. C. S. Kang, H. J. Cho, Y. H. Kim, R. Choi, K. Onishi, A. Shahriar, and J. C. Lee, "Characterization of resistivity and work function of sputtered-TaN film for gate electrode applications," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 21, pp. 2026-2028, 2003.
7. B. Y. Tsui and C. F. Huang, "Wide range work function modulation of binary alloys for MOSFET application," IEEE Electron Device Lett., vol. 24, pp. 153-155, Mar. 2003.
8. 2 gate dielectrics," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 21, pp. 11-17, 2003.
9. 2 gate stack," IEEE Electron Device Lett., vol. 25, pp. 123-125, Mar. 2004.
10. 2 gate stack for advanced MOS device applications," IEEE Electron Device Lett., vol. 25, pp. 70-72, Feb. 2004.
11. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, p. 75.
12. y metal gate electrodes," IEEE Electron Device Lett., vol. 24, pp. 439-441, July 2003.
13. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hedge, G. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi-level pinning at the polySi/metal oxide interface," in Symp. VLSI Tech. Dig., 2003, pp. 9-10.
14. x and metal gates," in IEDM Tech. Dig., 2003, pp. 307-310.