-
1
-
-
0025450664
-
A monolithic CMOS 10 MHz DPLL for burst-mode data retiming
-
J. Sonntag and R. Leonowich, "A monolithic CMOS 10 MHz DPLL for burst-mode data retiming," in IEEE ISSCC Dig. Tech. Papers, 1990, pp. 194-195.
-
(1990)
IEEE ISSCC Dig. Tech. Papers
, pp. 194-195
-
-
Sonntag, J.1
Leonowich, R.2
-
2
-
-
0028757753
-
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 Mbyte/s DRAM
-
Dec
-
T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, and T. Ishikawa, "A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 Mbyte/s DRAM," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1491-1496, Dec. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, Issue.12
, pp. 1491-1496
-
-
Lee, T.1
Donnelly, K.2
Ho, J.3
Zerbe, J.4
Johnson, M.5
Ishikawa, T.6
-
3
-
-
0031276490
-
A semidigital dual delay-locked loop
-
Nov
-
S. Sidiropoulos and M. Horowitz, "A semidigital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.11
, pp. 1683-1692
-
-
Sidiropoulos, S.1
Horowitz, M.2
-
4
-
-
0037888395
-
High performance inter-chip signalling,
-
Ph.D. dissertation, Stanford Univ, Stanford, CA
-
S. Sidiropoulos, "High performance inter-chip signalling," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1998.
-
(1998)
-
-
Sidiropoulos, S.1
-
5
-
-
39749107407
-
A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter
-
P. Hanumolu, V. Kratyuk, G. Wei, and U. Moon, "A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter," in Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 92-93.
-
(2006)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 92-93
-
-
Hanumolu, P.1
Kratyuk, V.2
Wei, G.3
Moon, U.4
-
7
-
-
39749147910
-
Improving CDR performance via estimation
-
H. Lee, A. Bansal, Y. Frans, J. Zerbe, S. Sidiropoulos, and M. Horowitz, "Improving CDR performance via estimation," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 1296-1303.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 1296-1303
-
-
Lee, H.1
Bansal, A.2
Frans, Y.3
Zerbe, J.4
Sidiropoulos, S.5
Horowitz, M.6
-
8
-
-
25844490996
-
Clocking and circuit design for a parallel I/O on a first-generation CELL processor
-
K. Chang et al., "Clocking and circuit design for a parallel I/O on a first-generation CELL processor," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 526-527.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 526-527
-
-
Chang, K.1
-
9
-
-
0036857082
-
Adaptive supply serial links with sub-1-V operation and per-pin clock recovery
-
Nov
-
J. Kim and M. Horowitz, "Adaptive supply serial links with sub-1-V operation and per-pin clock recovery," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1403-1413, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1403-1413
-
-
Kim, J.1
Horowitz, M.2
-
10
-
-
0033280776
-
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability
-
Dec
-
P. Larsson, "A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1951-1960, Dec. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.12
, pp. 1951-1960
-
-
Larsson, P.1
-
11
-
-
0032651134
-
Jitter and phase noise in ring oscillators
-
Jun
-
A. Hajimiri, S. Limotyrakis, and T. Lee, "Jitter and phase noise in ring oscillators," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 790-804, Jun. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.6
, pp. 790-804
-
-
Hajimiri, A.1
Limotyrakis, S.2
Lee, T.3
-
12
-
-
39749151119
-
A wide tracking range 0.2-4 Gbps clock and data recovery circuit
-
P. Hanumolu, G. Wei, and U. Moon, "A wide tracking range 0.2-4 Gbps clock and data recovery circuit," in Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 88-89.
-
(2006)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 88-89
-
-
Hanumolu, P.1
Wei, G.2
Moon, U.3
-
14
-
-
84996469077
-
Designing bang-bang PLLs for clock and data recovery in serial data transmission systems
-
B. Razavi, Ed. New York: Wiley-IEEE Press
-
R. Walker, "Designing bang-bang PLLs for clock and data recovery in serial data transmission systems," in Phase-Locking in High-Performanee Systems: From Devices to Architectures, B. Razavi, Ed. New York: Wiley-IEEE Press, 2003, pp. 34-45.
-
(2003)
Phase-Locking in High-Performanee Systems: From Devices to Architectures
, pp. 34-45
-
-
Walker, R.1
-
15
-
-
0242468194
-
A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization
-
Nov
-
B. Lee, M. Hwang, S. Lee, andD. Jeong, "A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1821-1829, Nov. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.11
, pp. 1821-1829
-
-
Lee, B.1
Hwang, M.2
Lee, S.3
andD4
Jeong5
-
16
-
-
0028733304
-
2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme
-
Dec
-
2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1482-1490, Dec. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, Issue.12
, pp. 1482-1490
-
-
Matsui, M.1
-
17
-
-
0342906692
-
Improved sense-amplifier-based flip-flop: Design and measurements
-
Jun
-
B. Nikolic et al, "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, Jun. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.6
, pp. 876-884
-
-
Nikolic, B.1
-
18
-
-
0016565959
-
Clock recovery from random binary signals
-
Oct
-
J. Alexander, "Clock recovery from random binary signals," Electron. Lett., pp. 541-542, Oct. 1975.
-
(1975)
Electron. Lett
, pp. 541-542
-
-
Alexander, J.1
-
19
-
-
0030188644
-
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS
-
Jul
-
J. Craninckx and M. Steyaert, "A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS," IEEE J. Solid-State. Circuits, vol. 31, no. 7, pp. 890-897, Jul. 1996.
-
(1996)
IEEE J. Solid-State. Circuits
, vol.31
, Issue.7
, pp. 890-897
-
-
Craninckx, J.1
Steyaert, M.2
-
20
-
-
0003457256
-
Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers,
-
Ph.D. dissertation, Mass. Inst. of Technol, Cambridge, MA
-
M. Perrott, "Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers," Ph.D. dissertation, Mass. Inst. of Technol., Cambridge, MA, 1997.
-
(1997)
-
-
Perrott, M.1
-
21
-
-
0034228929
-
A 5.3-GHz programmable divider for hiper-LAN in 0.25-μm CMOS
-
Jul
-
N. Krishnapura and P. Kinget, "A 5.3-GHz programmable divider for hiper-LAN in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1019-1024, Jul. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.7
, pp. 1019-1024
-
-
Krishnapura, N.1
Kinget, P.2
-
22
-
-
17044434982
-
An improved CMOS ring oscillator PLL with less than. 4 ps rms accumulated jitter
-
S. Williams, H. Thompson, M. Hufford, and E. Naviasky, "An improved CMOS ring oscillator PLL with less than. 4 ps rms accumulated jitter," in Proc. IEEE CICC, 2004, pp. 151-154.
-
(2004)
Proc. IEEE CICC
, pp. 151-154
-
-
Williams, S.1
Thompson, H.2
Hufford, M.3
Naviasky, E.4
-
23
-
-
38849089908
-
Phase Locked Loop With Control Voltage Centering,
-
U.S. Patent 6,826,246, Nov. 30
-
J. Brown and J. Sonntag, "Phase Locked Loop With Control Voltage Centering," U.S. Patent 6,826,246, Nov. 30, 2004.
-
(2004)
-
-
Brown, J.1
Sonntag, J.2
-
24
-
-
4744340842
-
Analysis of charge-pump phase-locked loops
-
Sep
-
P. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, "Analysis of charge-pump phase-locked loops," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 9, pp. 1665-1674, Sep. 2004.
-
(2004)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.51
, Issue.9
, pp. 1665-1674
-
-
Hanumolu, P.1
Brownlee, M.2
Mayaram, K.3
Moon, U.4
-
25
-
-
0036772590
-
Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops
-
Oct
-
M. Mansuri, D. Liu, and C. Yang, "Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops," IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 138-452, Oct. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.10
, pp. 138-452
-
-
Mansuri, M.1
Liu, D.2
Yang, C.3
-
26
-
-
17044424988
-
8 GHz, 20 mW, fast locking, fractional-N frequency synthesizer with, optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90 nm CMOS
-
A. Ravi, R. Bishop, L. Carley, and K. Soumyanath, "8 GHz, 20 mW, fast locking, fractional-N frequency synthesizer with, optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90 nm CMOS," in Proc. IEEE CICC, 2004, pp. 625-628.
-
(2004)
Proc. IEEE CICC
, pp. 625-628
-
-
Ravi, A.1
Bishop, R.2
Carley, L.3
Soumyanath, K.4
-
27
-
-
4544255406
-
A 0.6-4.2 V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nm CMOS process
-
P. Raha, "A 0.6-4.2 V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nm CMOS process," in Symp. VLSI Circuits Dig. Tech. Papers, 2004, pp. 232-235.
-
(2004)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 232-235
-
-
Raha, P.1
|