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Volumn 35, Issue 7, 2000, Pages 1019-1024

5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; FREQUENCY DIVIDING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SWITCHING CIRCUITS; VOLTAGE CONTROL;

EID: 0034228929     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.848211     Document Type: Article
Times cited : (77)

References (13)
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    • J. Craninckx and M. S. J. Steyaert, "A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS," IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 890-897, July 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , Issue.7 , pp. 890-897
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    • Digital multiphase clock/pattern generator
    • Feb.
    • F. Mu, et al., "Digital multiphase clock/pattern generator," IEEE J. Solid-State Circuits, vol. 34, pp. 182-191, Feb. 1999.
    • (1999) IEEE J. Solid-state Circuits , vol.34 , pp. 182-191
    • Mu, F.1
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    • Yuan, J.1    Svensson, C.2
  • 6
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    • Design of high-speed, low-power frequency dividers and phase locked loops in deep submicron CMOS
    • Feb.
    • B. Razavi, et al., "Design of high-speed, low-power frequency dividers and phase locked loops in deep submicron CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 101-109, Feb. 1995.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , pp. 101-109
    • Razavi, B.1
  • 9
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    • A single ended 1.5 GHz 8/9 dual modulus prescaler in 0.7μm CMOS technology with low phase noise and high input sensitivity
    • B. De Muer and M. Steyaert, "A single ended 1.5 GHz 8/9 dual modulus prescaler in 0.7μm CMOS technology with low phase noise and high input sensitivity," in Proc. 1998 Eur. Solid State Circuits Conf., 1998, pp. 256-259.
    • (1998) Proc. 1998 Eur. Solid State Circuits Conf. , pp. 256-259
    • De Muer, B.1    Steyaert, M.2
  • 11
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    • CMOS high-speed dual-modulus frequency divider tor RF frequency synthesis
    • Feb.
    • N. Foroudi and T. Kwasniewski, "CMOS high-speed dual-modulus frequency divider tor RF frequency synthesis," IEEE J. Solid-State Circuits, vol. 30, pp. 93-100, Feb. 1995.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , pp. 93-100
    • Foroudi, N.1    Kwasniewski, T.2
  • 12
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    • A 2 GHz CMOS dual-modulus prescalar IC
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  • 13
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    • Maeda, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.