Improving CDR performance via estimation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Lee, Haechang ^a   Bansal, Akash ^b   Frans, Yohan ^b   Zerbe, Jared ^b   Sidiropoulos, Stefanos ^c   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

^b Rambus   (United States)

^c Aeluros Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DAC CONTROL LOGIC; JITTER TOLERANCE;

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS; TIMING JITTER;

TIMING CIRCUITS;

EID: 39749147910     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)