Designing bang-bang PLLs for clock and data recovery in serial data transmission systems

Phase-Locking in High-Performance Systems: From Devices to Architectures

Volumn , Issue , 2003, Pages 34-45

  Walker, Richard C ^a  

^a AGILENT LABORATORIES   (United States)

Author keywords

Clocks; Detectors; Flip flops; Jitter; Phase locked loops; Time frequency analysis; Tracking loops

Indexed keywords

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS); CLOCKS; DATA COMMUNICATION SYSTEMS; DETECTORS; FLIP FLOP CIRCUITS; INFORMATION THEORY; JITTER; LOCKS (FASTENERS); NONLINEAR EQUATIONS; PHASE COMPARATORS; RECOVERY;

APPROXIMATE EQUATION; CLOCK AND DATA RECOVERY; MULTI-PHASE SAMPLING; PHASE LOCKED LOOP (PLL); SERIAL DATA TRANSMISSIONS; TIME FREQUENCY ANALYSIS; TRACKING LOOP; TRACKING PERFORMANCE;

PHASE LOCKED LOOPS;

EID: 84996469077     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470545492.ch4     Document Type: Chapter

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