A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 7, 1996, Pages 890-897

  Craninckx, Jan ^b   Steyaert, Michiel S J ^a,b,c,d  

^a IEEE

^b UNIVERSITY OF LEUVEN   (Belgium)

^c Laboratory ESAT

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EFFICIENCY; ELECTRIC FREQUENCY MEASUREMENT; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUIT LAYOUT; PERFORMANCE; PHASE LOCKED LOOPS;

DUAL MODULUS PRESCALER; MAXIMUM INPUT FREQUENCY; POWER SUPPLY VOLTAGE; SYNCHRONOUS DIVIDER;

FREQUENCY DIVIDING CIRCUITS;

EID: 0030188644     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508200     Document Type: Article

References (7)

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