Analysis of charge-pump phase-locked loops

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 9, 2004, Pages 1665-1674

  Hanumolu, Pavan Kumar ^a   Brownlee, Merrick ^a   Mayaram, Kartikeya ^a   Moon, Un Ku ^a  

^a 1148 Kelley Engineering Center Corvallis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; JITTER; NONLINEAR EQUATIONS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; STATE SPACE METHODS; VARIABLE FREQUENCY OSCILLATORS; Z TRANSFORMS;

IMPULSE INVARIANCE; LOOP DELAY; PHASE NOISE; STATE SPACE; Z-DOMAIN;

ELECTRIC NETWORK ANALYSIS;

EID: 4744340842     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.834516     Document Type: Article

References (18)

1. I. Young, J. Greason, and K. Wong, "PLL clock generator with 5 to 10 MHz of lock range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
2. H. Ahn and D. Allstot, "A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications," IEEE J. Solid-State Circuits, vol. 35, pp. 450-454, Mar. 2000.
3. V. Kaenel, "A high-speed, low-power clock generator for a microprocessor application," IEEE J. Solid-State Circuits, vol. 33, pp. 1634-1639, Nov. 1998.
4. H. Rategh, H. Samavati, and T. Lee, "A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver," IEEE J. Solid-State Circuits, vol. 35, pp. 780-787, May 2000.
5. J. Craninckx and M. Steyaert, "A fully integrated CMOS DCS-1800 frequency synthesizer," IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998.
6. M. Meghelli, B. Parker, H. Ainspan, and M. Soyuer, "SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems," IEEE J. Solid-State Circuits, vol. 35, pp. 1992-1995, Dec. 2000.
7. K. Lee, S. Kim, G. Ahn, and D. Jeong, "A CMOS serial link for fully duplexed data communication," IEEE J. Solid-State Circuits, vol. 30, pp. 353-364, Apr. 1995.
8. S. Miyazawa, R. Horita, K. Hase, K. Kato, and S. Kojima, "A BiCMOS PLL-based data separator circuit with high stability and accuracy," IEEE J. Solid-State Circuits, vol. 26, pp. 116-121, Feb. 1991.
9. J. Hein and J. Scott, "z-domain model for discrete-time PLLs," IEEE Trans. Circuits Syst., vol. 35, pp. 1393-1400, Nov. 1988.
10. F. Gardner, "Charge pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov 1980.
11. I. Novof, J. Austin, R. Kelkar, D. Strayer, and S. Wyatt, "Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter," IEEE J. Solid-State Circuits, vol. 30, pp. 1259-1266, Nov. 1995.
12. J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
13. M. Perrott, "Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits," in Proc. Design Automation Conf., June 2002, pp. 498-503.
14. V. von Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, "A 320 MHz, 1.5 mW 1.35 V CMOS PLL for microprocessor clock generation," IEEE J. Solid-State Circuits, vol. 31, pp. 1715-1722, Nov 1996.
15. H. Yang, K. Lee, and R. Co, "A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation," IEEE J. Solid-State Circuits, vol. 32, pp. 582-586, Apr. 1997.
16. L. Lin, L. Tee, and P. Gray, "A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture," Dig. Tech. Papers ISSCC, pp. 204-205, Feb. 2000.
17. M. Perrott, T. Tewksbury, and C. Sodini, "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997.
18. C. Chen, Linear System Theory and Design, 3rd ed. Oxford, U.K.: Oxford University Press, 1999.