Energy-efficient and high-performance instruction fetch using a block-aware ISA

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 36-41

  Zmily, Ahmad ^a   Kozyrakis, Christos ^a  

^a Stanford University   (United States)

Author keywords

Basic blocks; Decoupled architecture; Energy efficiency; Instruction delivery; Instruction set architecture

Indexed keywords

BUFFER STORAGE; ENERGY EFFICIENCY; ENERGY UTILIZATION; POWER ELECTRONICS;

BASIC BLOCKS; DECOUPLED ARCHITECTURE; INSTRUCTION DELIVERY; INSTRUCTION SET ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 28444463705     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195482     Document Type: Conference Paper

References (24)

1. W. M. Felter et al. On The Performance and Use of Dense Servers. IBM J. RES. and DEV., 47(5/6), September 2003.
2. R. Ronen, A. Mendelson, et al. Coming Challenges in Microarchitecture and Architecture. Proceedings of the IEEE, 89(3), March 2001.
3. Kanad Ghose and Milind B. Ramble. Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit-line Segmentation. In Intl. Symposium on Low Power Electronics and Design, San Diego, CA, August 1999.
4. Glenn Reinman, Brad Calder, and Todd M. Austin. High Performance and Energy Efficient Serial Prefetch Architecture. In Intl. Symposium on High Performance Computing, Kansai Science City, Japan, May 2002.
5. A. Ramirez, J. Larriba-Pey, and M. Valero. Branch Prediction Using Profile Data. In EuroPar Conference, Manchester, UK, August 2001.
6. S. Melvin and Y. Patt. Enhancing Instruction Scheduling with a Block-structured ISA. Intl. Journal on Parallel Processing, 23(3), June 1995.
7. T. Chen and J.L. Baer. A Performance Study of Software and Hardware Data Prefetching Schemes. In Intl. Symposium on Computer Architecture, Chicago, IL, April 1994.
8. G. Reinman, B. Calder, and T. Austin. Fetch Directed Instruction Prefetching. In Intl. Symposium on Microarchitecture, Haifa, Israel, November 1999.
9. G. Reinman, C. Calder, and T. Austin. Optimizations Enabled by a Decoupled Front-End Architecture. IEEE TC, 50(40), April 2001.
10. D. Burger and M. Austin. Simplescalar Tool Set, Version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
11. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In Intl. Symposium on Computer Architecture, Vancouver, BC, Canada, June 2000.
12. M. Powell et al. Reducing Set-Associative Cache Energy via Way Prediction and Selective Direct-Mapping. In Intl. Symposium on Microarchitecture, Austin, Texas, December 2001.
13. David H. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. In Intl. Symposium on Microarchitecture, Haifa, Israel, November 1999.
14. Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco Barcella, and Mircea R. Stan. Power Issues Related To Branch Prediction. In Intl. Symposium on High-Performance Computer Architecture, Boston, MA, February 2001.
15. A. Baniasadi and A. Moshovos. Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. In Intl. Conference on Computer Design, Freiburg, Germany, September 2002.
16. J. Aragon, J. Gonzalez, and A. Gonzalez. Power-Aware Control Speculation Through Selective Throttling. In Intl. Symposium on High-Performance Computer Architecture, Anaheim, CA, February 2003.
17. R. Wedig and M. Rose. The Reduction of Branch Instruction Execution Overhead Using Structured Control Flow. In Intl. Symposium on Computer Architecture, Ann Arbor, MI, June 1984.
18. V. Kathail, M. Schlansker, and B. Rau. HPL PlayDoh Architecture Specification. Technical Report HPL-93-80, HP Labs, 1994.
19. T. Yeh and Y. Patt. A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution. In Intl. Symposium on Microarchitecture, Portland, OR, December 1992.
20. B. Calder and D. Grunwald. Fast and Accurate Instruction Fetch and Branch Prediction. In Intl. Symposium on Computer Architecture, Chicago, IL, April 1994.
21. J. Stark, P. Racunas, and Y. Patt. Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. In Intl. Symposium on Microarchitecture, Research Triangle Park, NC, December 1997.
22. D. Friendly, S. Patel, and Y. Patt. Alternative Fetch and Issue Techniques from the Trace Cache Mechanism. In Intl. Symposium on Microarchitecture, Research Triangle Park, NC, December 1997.
23. S. Patel, M. Evers, and Y. Patt. Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. In Intl. Symposium on Computer Architecture, Barcelona, Spain, June 1998.
24. S. Jourdan et al. Extended Block Cache. In Intl. Symposium on High-Performance Computer Architecture, Toulouse, France, January 2000.