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Volumn 1, Issue , 2006, Pages
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Simultaneously improving code size, performance, and energy in embedded processors
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Author keywords
[No Author keywords available]
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Indexed keywords
CODES (SYMBOLS);
COMPUTER ARCHITECTURE;
EMBEDDED SYSTEMS;
SYSTEMS ANALYSIS;
BLOCK-AWARE INSTRUCTION SETS (BLISS);
DECOMPRESSION LATENCY;
EMBEDDED PROCESSORS;
MICROPROCESSOR CHIPS;
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EID: 34047132853
PISSN: 15301591
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/date.2006.244090 Document Type: Conference Paper |
Times cited : (8)
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References (22)
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