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Volumn 3648, Issue , 2005, Pages 530-539

Improving instruction delivery with a block-aware ISA

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; COMPUTER HARDWARE;

EID: 27144474555     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11549468_60     Document Type: Conference Paper
Times cited : (2)

References (21)
  • 1
    • 84948758906 scopus 로고    scopus 로고
    • Coming challenges in microarchitecture and architecture
    • March
    • R. Ronen, A. Mendelson, et al. Coming Challenges in Microarchitecture and Architecture. Proceedings of the IEEE, 89(3), March 2001.
    • (2001) Proceedings of the IEEE , vol.89 , Issue.3
    • Ronen, R.1    Mendelson, A.2
  • 3
    • 0035308287 scopus 로고    scopus 로고
    • Optimizations enabled by a decoupled front-end architecture
    • April
    • G. Reinman, C. Calder, and T. Austin. Optimizations Enabled by a Decoupled Front-End Architecture. IEEE TC, 50(40), April 2001.
    • (2001) IEEE TC , vol.50 , Issue.40
    • Reinman, G.1    Calder, C.2    Austin, T.3
  • 5
    • 0029326787 scopus 로고
    • Enhancing instruction scheduling with a block-structured ISA
    • June
    • S. Melvin and Y. Patt. Enhancing Instruction Scheduling with a Block-structured ISA. Intl. Journal on Parallel Processing, 23(3), June 1995.
    • (1995) Intl. Journal on Parallel Processing , vol.23 , Issue.3
    • Melvin, S.1    Patt, Y.2
  • 6
    • 0028202735 scopus 로고
    • A performance study of software and hardware data prefetching schemes
    • Chicago, IL, April
    • T. Chen and J.L. Baer. A Performance Study of Software and Hardware Data Prefetching Schemes. In Intl. Symposium on Computer Architecture, Chicago, IL, April 1994.
    • (1994) Intl. Symposium on Computer Architecture
    • Chen, T.1    Baer, J.L.2
  • 7
    • 0034226001 scopus 로고    scopus 로고
    • SPEC CPU2000: Measuring performance in the new millennium
    • July
    • J. Henning. SPEC CPU2000: Measuring Performance in the New Millennium. IEEE Computer, 33(7), July 2000.
    • (2000) IEEE Computer , vol.33 , Issue.7
    • Henning, J.1
  • 9
    • 0003465202 scopus 로고    scopus 로고
    • Simplescalar tool set, version 2.0
    • University of Wisconsin, Madison, June
    • D. Burger and M. Austin. Simplescalar Tool Set, Version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
    • (1997) Technical Report , vol.CS-TR-97-1342
    • Burger, D.1    Austin, M.2
  • 10
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • Vancouver, BC, Canada, June
    • D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In Intl. Symposium on Computer Architecture, Vancouver, BC, Canada, June 2000.
    • (2000) Intl. Symposium on Computer Architecture
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 11
    • 0021177458 scopus 로고
    • The reduction of branch instruction execution overhead using structured control flow
    • Ann Arbor, MI, June
    • R. Wedig and M. Rose. The Reduction of Branch Instruction Execution Overhead Using Structured Control Flow. In Intl. Symposium on Computer Architecture, Ann Arbor, MI, June 1984.
    • (1984) Intl. Symposium on Computer Architecture
    • Wedig, R.1    Rose, M.2
  • 12
    • 0004049308 scopus 로고
    • HPL PlayDoh architecture specification
    • HP Labs
    • V. Kathail, M. Schlansker, and B. Rau. HPL PlayDoh Architecture Specification. Technical Report HPL-93-80, HP Labs, 1994.
    • (1994) Technical Report , vol.HPL-93-80
    • Kathail, V.1    Schlansker, M.2    Rau, B.3
  • 14
    • 27144512535 scopus 로고    scopus 로고
    • The branch processor architecture
    • Cornell Computer Systems Laboratory, November
    • R. Manohar and M. Heinrich. The Branch Processor Architecture. Technical Report CSL-TR-1999-1000, Cornell Computer Systems Laboratory, November 1999.
    • (1999) Technical Report , vol.CSL-TR-1999-1000
    • Manohar, R.1    Heinrich, M.2
  • 15
    • 0026961839 scopus 로고
    • A comprehensive instruction fetch mechanism for a processor supporting speculative execution
    • Portland, OR, December
    • T. Yeh and Y. Patt. A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution. In Intl. Symposium on Microarchitecture, Portland, OR, December 1992.
    • (1992) Intl. Symposium on Microarchitecture
    • Yeh, T.1    Patt, Y.2
  • 16
  • 17
    • 0031333687 scopus 로고    scopus 로고
    • Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order
    • Research Triangle Park, NC, December
    • J. Stark, P. Racunas, and Y. Patt. Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. In Intl. Symposium on Microarchitecture, Research Triangle Park, NC, December 1997.
    • (1997) Intl. Symposium on Microarchitecture
    • Stark, J.1    Racunas, P.2    Patt, Y.3
  • 18
    • 27144488257 scopus 로고    scopus 로고
    • Alternative fetch and issue techniques from the trace cache mechanism
    • Research Triangle Park, NC, December
    • D. Friendly, S. Patel, and Y. Patt. Alternative Fetch and Issue Techniques from the Trace Cache Mechanism. In Intl. Symposium on Microarchitecture, Research Triangle Park, NC, December 1997.
    • (1997) Intl. Symposium on Microarchitecture
    • Friendly, D.1    Patel, S.2    Patt, Y.3
  • 20
    • 0031594002 scopus 로고    scopus 로고
    • Improving trace cache effectiveness with branch promotion and trace packing
    • Barcelona, Spain, June
    • S. Patel, M. Evers, and Y. Patt. Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. In Intl. Symposium on Computer Architecture, Barcelona, Spain, June 1998.
    • (1998) Intl. Symposium on Computer Architecture
    • Patel, S.1    Evers, M.2    Patt, Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.