Architecture-level power optimization - What are the limits?

Journal of Instruction-Level Parallelism

Volumn 7, Issue , 2005, Pages

  Seng, John S ^a   Tullsen, Dean M ^b  

^a CALIFORNIA POLYTECHNIC STATE UNIVERSITY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 24144497107     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (41)

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