메뉴 건너뛰기




Volumn 2, Issue 4, 2003, Pages 449-481

Tiny Instruction Caches For Low Power Embedded Systems

Author keywords

architecture tuning; Design; embedded systems; filter cache; fixed program; instruction cache; Loop cache; low energy; low power

Indexed keywords


EID: 84966499492     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/950162.950163     Document Type: Article
Times cited : (22)

References (25)
  • 7
    • 0003510233 scopus 로고    scopus 로고
    • Evaluating future microprocessors: the simplescalar toolset
    • University of Wisconsin-Madison. Computer Science Department. Tech. Report CS-TR-1308
    • Burger, D., Austin, T, Bennet, S., 1996. Evaluating future microprocessors: the simplescalar toolset. University of Wisconsin-Madison. Computer Science Department. Tech. Report CS-TR-1308.
    • (1996)
    • Burger, D.1    Austin, T.2    Bennet, S.3
  • 12
    • 21044436759 scopus 로고    scopus 로고
    • A power reduction technique with object code merging for application specific embedded processors
    • Ishihara, Y., Yasuura, H., 2000. A power reduction technique with object code merging for application specific embedded processors. In Design Automation and Test in Europe.
    • (2000) Design Automation and Test in Europe.
    • Ishihara, Y.1    Yasuura, H.2
  • 13
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • Jouppi, N., 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In International Symposium on Computer Architecture, 364-373.
    • (1990) International Symposium on Computer Architecture , pp. 364-373
    • Jouppi, N.1
  • 18
    • 85024254908 scopus 로고    scopus 로고
    • Data processing system having a cache and method
    • there of, US Patent number 5, 893, 142
    • Moyer, B., Lee, L. H., Arends, J., 1999. Data processing system having a cache and method there of, US Patent number 5, 893, 142.
    • (1999)
    • Moyer, B.1    Lee, L.H.2    Arends, J.3
  • 22
    • 4243397947 scopus 로고
    • Efficient simulation of multiple cache configurations using binomial trees
    • Technical Report CSE-TR-111-91, CSE Division, University of Michigan
    • Sugumar, R., Abraham, S., 1991. Efficient simulation of multiple cache configurations using binomial trees. Technical Report CSE-TR-111-91, CSE Division, University of Michigan.
    • (1991)
    • Sugumar, R.1    Abraham, S.2
  • 23
    • 0003485603 scopus 로고    scopus 로고
    • Loop analysis of embedded applications
    • UC Riverside CS&E Technical Report UCR-CSE-01-03
    • Villarreal, J., Lysecky, R., Cotterell, S., Vahid, F. n.d., Loop analysis of embedded applications. UC Riverside CS&E Technical Report UCR-CSE-01-03.
    • Villarreal, J.1    Lysecky, R.2    Cotterell, S.3    Vahid, F.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.