Multiple-gate CMOS thin-film ransistor with polysilicon nanowire

IEEE Electron Device Letters

Volumn 29, Issue 1, 2008, Pages 102-105

  Im, Maesoon ^a   Han, Jim Woo ^a   Lee, Hyunjin ^a   Yu, Lee Eun ^a   Kim, Sungho ^a   Kim, Chang Hoon ^b   Jeon, Sang Cheol ^b   Kim, Kwang Hee ^a   Lee, Gi Sung ^b   Oh, Jae Sub ^b   Park, Yun Chang ^b   Lee, Hee Mok ^b   Choi, Yang Kyu ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b National Nano Fab Center (NNFC)   (South Korea)

Author keywords

CMOS; Multiple gate; Nanoscale; Nanowire; Thin film transistor (TFT); Vertical integration

Indexed keywords

CRYSTALLIZATION; GATES (TRANSISTOR); NANOWIRES; POLYSILICON; THIN FILM TRANSISTORS;

MULTIPLE-GATE CMOS THIN-FILM TRANSISTOR; NANOSCALE; POLYSILICON NANOWIRE; TERABIT MEMORY; VERTICAL INTEGRATION;

CMOS INTEGRATED CIRCUITS;

EID: 37549041289     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.911982     Document Type: Article

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