A new polysilicon CMOS self-aligned double-gate TFT technology

IEEE Transactions on Electron Devices

Volumn 52, Issue 12, 2005, Pages 2629-2633

  Xiong, Zhibin ^a   Liu, Haitao ^b   Zhu, Chunxiang ^c   Sin, Johnny K O ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b MICRON TECHNOLOGY INC   (United States)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

CMOS; Double gate (DG); Polysilicon thin film trans stor (TFT); Self aligned (SA)

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELD MEASUREMENT; ELECTRON DENSITY MEASUREMENT; GATES (TRANSISTOR); POLYSILICON; THIN FILM TRANSISTORS;

BACKLIGHT EXPOSURE; CURRENT SATURATION; DOUBLE-GATE (DG); SELF-ALIGNED (SA); ULTRATHIN CHANNEL REGION;

CMOS INTEGRATED CIRCUITS;

EID: 29244445531     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.859686     Document Type: Article

References (16)

1. K. Werner, "The flowering of flat displays," IEEE Spectr., vol. 34, no. 5, pp. 40-49, May 1997.
2. M. Stewart, R. Howell, L. Pires, M. Hatalis, W. Howard, and O. Prache, "Poly Si VGA active matrix OLED displays technology and performance," in IEDM Tech. Dig., 1998, pp. 871-874.
3. A. Kumar and J. K. O. Sin, "A simple polysilicon TFT technology for display systems on glass," in IEDM Tech. Dig., 1997, pp. 515-518.
4. A. G. Lewis, D. D. Lee, and R. H. Bruce, "Polysilicon TFT circuit design and performance," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1833-1842, Dec. 1992.
5. H. G. Yang, S. Fluxman, C. Reita, and P. Migliorato, "Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers," IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 727-732, Jun. 1994.
6. J. Jang, J. Y. Oh, and S. K. Kim, "Electric-field-enhanced crystallization of amorphous silicon," Nature, vol. 395, no. 6701, pp. 481-483, 1998.
7. K. Ohgata, Y. Mishima, and N. Sasaki, "A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structure," in 1EDM Tech. Dig., 2000, pp. 205-208.
8. C. W. Lin, C. H. Tseng, T. K. Chang, C. W. Lin, W. T. Wang, and H. C. Cheng, "A novel laser-processed self-aligned gate-overlapped LDD poly-Si TFT," IEEE Electron Device Lett., vol. 23, no. 3, pp. 133-135, Mar. 2002.
9. H. Huriyama, Y. Ishigaki, Y. Fujii, S. Maegawa, S. Mäeda, S. Miyamoto, K. Tsutsumi, H. Miyoshi, and A. Yasuoka, "A C-switch cell for low-voltage and high-density SRAMs," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2483-2488, Dec. 1998.
10. K. P. A. Kumar, J. K. O. Sin, C. T. Nguyen, and P. K. Ko, "Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2514-2520, Dec. 1998.
11. S. Zhang, R. Han, J. K. O. Sin, and M. Chan, "Implementation and characterization of self-aligned double-gate TFT with thin channel and thick source/drain," IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 718-724, May 2002.
12. A. Hara, M. Takei, K. Yoshino, F. Takeuchi, M. Chida, and N. Sasaki, "Self-aligned top and bottom metal double gate low temperature poly-Si TFT fabricated at 500 °C on nonalkali glass substrate by using DPSS CW laser lateral crystallization method," in IEDM Tech. Dig., 2003, pp. 211-214.
13. Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, "A simple CMOS self-aligned double-gate poly-Si TFT technology," in Proc. 7th Int. Symp. Thin Film Transistor Technologies, 2004, pp. 123-127.
14. MEDICI Users Manual, Avant! Corporation, Fremont, CA, 2001.
15. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, T. Taur, and H. S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
16. Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, "A novel self-aligned ultrathin elevated channel low temperature CMOS poly-Si TFT," in Proc. 6th Int. Symp. Thin Film Transistor Technologies, Salt Lake City, UT, 2002, pp. 42-46