Short-channel amorphous-silicon thin-film transistors

IEEE Transactions on Electron Devices

Volumn 43, Issue 12, 1996, Pages 2172-2176

  Kim, Chang Dong ^a   Matsumura, Masakiyo ^b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b LG Electronics Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SILICON; CRYSTALLIZATION; ELECTRIC RESISTANCE; ELECTRODES; ELECTRON TRANSPORT PROPERTIES; ELECTRONIC PROPERTIES; EXCIMER LASERS; GATES (TRANSISTOR); POLYCRYSTALLINE MATERIALS; SEMICONDUCTING FILMS; SEMICONDUCTOR DEVICE MANUFACTURE; TRANSMISSION ELECTRON MICROSCOPY;

AMORPHOUS SILICON THIN FILM TRANSISTORS; ELECTRODE THICKNESS; EXCIMER LASER CRYSTALLIZATION; MOBILITY; POLYSILICON LAYERS;

THIN FILM TRANSISTORS;

EID: 0030378323     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.544388     Document Type: Article

References (12)

1. Y. Uchida and M. Matsumura, "Short-channel a-Si thin-film MOS transistors," IEEE Trans. Electron Devices, vol. 36, no. 12. pp. 2940-2943, 1989.
2. H. H. Busta, J. E. Pogemiller, R. W. Standley, and K. D. Mackenzie, "Self-aligned bottom-gate submicrometer-channel-length a-si : H thin-film transistors," IEEE Trans. Electron Devices, vol. 36, no. 12, pp. 2883-2888, 1989.
3. O. Sugiura, C. D. Kim, and M. Matsumura, "New self-alignment processes for amorphous-silicon thin film transistors with polysilicon source and drain," Electron. Lett., vol. 29, no. 9, pp. 750-752, 1993.
4. C. D. Kim, O. Sugiura, and M. Matsumura, "Amorphous-silicon TFT's with self-aligned poly-silicon source and drain," in Proc. Mat. Res. Soc. Symp., 1993, vol. 297, pp. 925-930.
5. B. C. Ahn, K. Shimizu, T. Satoh, H. Kanoh, O. Sugiura, and M. Matsumura, "Hot-wall chemical vapor deposition of amorphous-silicon and its application to thin-film transistors," Jpn. J. Appl. Phys., vol. 30, no. 12B, pp. 3695-3699, 1991.
6. O. Sugiura, T. Shiraiwa, and M. Matsumura, "A novel post-hydrogenation process for chemical-vapor-deposited a-Si thin-film transistors,'" Jpn. J. Appl. Phys., vol. 32, no. 7B, pp. L981-L983, 1993.
7. J. G. Shaw and M. Hack, "Simulations of short-channel and overlap effects in amorphous silicon thin-film transistors," J. Appl. Phys., vol. 65, no. 5, pp. 2124-2129, 1989.
8. M. Hack, M. S. Shur, and J. G. Shaw, "Physical models for amorphoussilicon thin-film transistors and their implementation in a circuit simulation program," IEEE Trans. Electron Devices, vol. 36. no. 12, pp. 2764-2768, 1989.
9. S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, "Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor." IEEE Trans. Electron Devices, vol. 27, no. 8, pp. 1359-1367, 1980.
10. C.-D. Kim and M. Matsumura, "Amorphous-silicon distributed-threshold voltage transistors with self-aligned poly-silicon sources and drains." IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1614-1617, 1994.
11. M. Hack, J. G. Shaw, and M. Shur, "Simulation and physics of amorphous silicon thin-film transistors," J. Non-Cryst. Solids, vol. 115, pp. 150-158, 1989.
12. N. Hirose, Y. Uchida, and M. Matsumura, "Two-dimensional numerical analysis of amorphous-silicon field-effect transistors." Jpn. J. Appl. Phys., vol. 24, pp. 200-207, 1985.