A 5GHz+ 128-bit binary floating-point adder for the POWER6 processor

ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Volumn , Issue , 2006, Pages 166-169

  Yu, Xiao Yan ^a   Chan, Yiu Hing ^a   Curran, Brian ^a   Schwarz, Eric ^a   Kelly, Michael ^a   Fleischer, Bruce ^b  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOATING-POINT DESIGN; STATIC CIRCUITS;

DIGITAL ARITHMETIC; INTEGRATED CIRCUITS;

ADDERS;

EID: 37549009215     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2006.307557     Document Type: Conference Paper

References (20)