Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors

IBM Journal of Research and Development

Volumn 49, Issue 1, 2005, Pages 167-188

  Buti, Taqi N ^a   McDonald, Robert G ^b   Khwaja, Zakaria ^a   Ambekar, Asit ^a   Le, H Q ^a   Burky, W E ^a   Williams, B ^a  

^a IBM   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; DATA STORAGE EQUIPMENT; LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER);

CONTENT ADDRESSABLE MEMORY; REGISTER MAPPERS; SOURCE LOOKUP; VECTORED ALLOCATION BUFFERS;

MICROPROCESSOR CHIPS;

EID: 13844255383     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.491.0167     Document Type: Article

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