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Volumn 51, Issue 6, 2007, Pages 663-683

IBM POWER6 accelerators: VMX and DFU

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; GRAPHIC METHODS; MULTIMEDIA SYSTEMS; SOFTWARE ARCHITECTURE;

EID: 37549031291     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.516.0663     Document Type: Article
Times cited : (77)

References (17)
  • 1
    • 37549046115 scopus 로고    scopus 로고
    • Freescale Semiconductor, AltiVec™ Technology Programming Environments Manual, 2006; see http://www.freescale.com/files/ 32bit/doc/ref_manual/ALTIVECPEM.pdf.
    • Freescale Semiconductor, AltiVec™ Technology Programming Environments Manual, 2006; see http://www.freescale.com/files/ 32bit/doc/ref_manual/ALTIVECPEM.pdf.
  • 5
    • 37549013032 scopus 로고    scopus 로고
    • S. D. Trong, M. Schmookler, E. M. Schwarz, and M. Kroener, POWER6 Binary Floating-Point Unit, Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH18), Montpellier, France, 2007, pp. 77-86.
    • S. D. Trong, M. Schmookler, E. M. Schwarz, and M. Kroener, "POWER6 Binary Floating-Point Unit," Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH18), Montpellier, France, 2007, pp. 77-86.
  • 6
    • 0003589321 scopus 로고
    • IEEE Standard for Binary Floating-Point Arithmetic
    • IEEE; see
    • ANS1/IEEE Standard 754-1985, "IEEE Standard for Binary Floating-Point Arithmetic," ©1985 IEEE; see http:// 754r.ucbtest.org/standards/754xml.html.
    • (1985) ANS1/IEEE Standard 754-1985
  • 9
    • 36049052267 scopus 로고    scopus 로고
    • Binary Floating-Point Unit Design: The Fused Multiply-Add Dataflow
    • V. G. Oklobdzija and R. K. Krishnamurthy, Eds, Springer, Dordrecht, The Netherlands
    • E. M. Schwarz, "Binary Floating-Point Unit Design: The Fused Multiply-Add Dataflow," High-Performance Energy-Efficient Microprocessor Design, V. G. Oklobdzija and R. K. Krishnamurthy, Eds., Springer, Dordrecht, The Netherlands, 2006, pp. 189-208.
    • (2006) High-Performance Energy-Efficient Microprocessor Design , pp. 189-208
    • Schwarz, E.M.1
  • 11
    • 33645675534 scopus 로고    scopus 로고
    • A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a Cell Processor
    • H.-J. Oh, S. M. Mueller, C. Jacobi, K. D. Tran, S. R. Cottier, B. W. Michael, H. Nishikawa, et al., "A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a Cell Processor," IEEE J. Solid-State Circuits 41, No. 4, 759-771 (2006).
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.4 , pp. 759-771
    • Oh, H.-J.1    Mueller, S.M.2    Jacobi, C.3    Tran, K.D.4    Cottier, S.R.5    Michael, B.W.6    Nishikawa, H.7
  • 12
    • 37549018196 scopus 로고    scopus 로고
    • ANSI/IEEE, DRAFT Standard for Floating-Point Arithmetic P754, Draft 1.2.5, see Working Group Records, at http://754r.ucbtest.org/.
    • ANSI/IEEE, "DRAFT Standard for Floating-Point Arithmetic P754," Draft 1.2.5, see "Working Group Records," at http://754r.ucbtest.org/.
  • 15
    • 0003589325 scopus 로고
    • IEEE Standard for Radix-Independent Floating-Point Arithmetic
    • IEEE; see
    • ANSI/IEEE Standard 854-1987, "IEEE Standard for Radix-Independent Floating-Point Arithmetic," ©1987 IEEE; see http://754r.ucbtest.org/Standards/854xml.html.
    • (1987) ANSI/IEEE Standard 854-1987
  • 16
    • 37548999071 scopus 로고    scopus 로고
    • submitted to the 18th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Montreal, Canada, July
    • E. M. Schwarz and S. Carlough, "POWER6 Decimal Divide," submitted to the 18th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Montreal, Canada, July 2007.
    • (2007) POWER6 Decimal Divide
    • Schwarz, E.M.1    Carlough, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.