-
2
-
-
0022061669
-
Optimal interconnection circuits for VLSI
-
2
-
[2[ H.B. Bakoglu & J.D. Meindl, Optimal interconnection circuits for VLSI, IEEE Transactions on Electron Devices, ED-32(5), 1985, 903-909.
-
(1985)
IEEE Transactions on Electron Devices
, vol.ED-32
, Issue.5
, pp. 903-909
-
-
Bakoglu, H.B.1
Meindl, J.D.2
-
3
-
-
0003479594
-
Circuits, interconnections and packaging for VLSI, VLSI Systems
-
Reading, MA: Addison Wesley
-
H.B. Bakoglu, Circuits, interconnections and packaging for VLSI, VLSI Systems Series (Reading, MA: Addison Wesley, 1990).
-
(1990)
Series
-
-
Bakoglu, H.B.1
-
4
-
-
0033891230
-
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
-
4
-
[4[ Y.I. Ismail & E.G. Friedman, Effects of inductance on the propagation delay and repeater insertion in VLSI circuits, IEEE Transactions on VLSI Systems, 8(2), 2000, 195-206.
-
(2000)
IEEE Transactions on VLSI Systems
, vol.8
, Issue.2
, pp. 195-206
-
-
Ismail, Y.I.1
Friedman, E.G.2
-
5
-
-
0034790238
-
Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling
-
K. Banerjee & A. Mehrotra, Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling, Proc. Symp. on VLSI Circuits Digest of Technical Papers, 2001, 18-1, 195-198.
-
(2001)
Proc. Symp. on VLSI Circuits Digest of Technical Papers
-
-
Banerjee, K.1
Mehrotra, A.2
-
6
-
-
36949000851
-
-
ITRS 2001 to 2003. Website: http://public.itrs.net
-
ITRS 2001 to 2003. Website: http://public.itrs.net
-
-
-
-
7
-
-
0025507597
-
Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters
-
C.Y. Wu & M.C. Shiau, Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters, IEEE Journal of Solid State Circuits, 25(5), 1990, 1247-1256.
-
(1990)
IEEE Journal of Solid State Circuits
, vol.25
, Issue.5
, pp. 1247-1256
-
-
Wu, C.Y.1
Shiau, M.C.2
-
8
-
-
0025953236
-
Optimum buffer circuits for driving long uniform lines
-
S. Dhar & M.A. Franklin, Optimum buffer circuits for driving long uniform lines, IEEE Journal of Solid State Circuits, 26(1), 1991, 32-40.
-
(1991)
IEEE Journal of Solid State Circuits
, vol.26
, Issue.1
, pp. 32-40
-
-
Dhar, S.1
Franklin, M.A.2
-
9
-
-
0028752921
-
A variable-size parallel regenerator for long integrated interconnections
-
M. Nekili, Y. Savaria, & G. Bios, A variable-size parallel regenerator for long integrated interconnections, Proc. 37th Midwest Symp. on Circuits and Systems, 1, 1994, 50-53.
-
(1994)
Proc. 37th Midwest Symp. on Circuits and Systems
, vol.1
, pp. 50-53
-
-
Nekili, M.1
Savaria, Y.2
Bios, G.3
-
10
-
-
0032072770
-
Repeater design to reduce delay and power in resistive interconnects
-
V. Adler & E.G. Friedman, Repeater design to reduce delay and power in resistive interconnects, IEEE Transactions on Circuits and Systems. II: Analog and Digital Signal Processing, 45(5), 1998, 607-616.
-
(1998)
IEEE Transactions on Circuits and Systems. II: Analog and Digital Signal Processing
, vol.45
, Issue.5
, pp. 607-616
-
-
Adler, V.1
Friedman, E.G.2
-
11
-
-
13844272354
-
Repeater insertion in global interconnects in VLSI circuits
-
R. Chandel, S. Sarkar, & R.P. Agarwal, Repeater insertion in global interconnects in VLSI circuits, Microelectronics International, 22(1), 2005, 43-50.
-
(2005)
Microelectronics International
, vol.22
, Issue.1
, pp. 43-50
-
-
Chandel, R.1
Sarkar, S.2
Agarwal, R.P.3
-
12
-
-
33747566850
-
3D ICs: A novel chip design for improving deep submicrometer interconnect performance and system-on-chip integration
-
K. Banerjee, S.J. Souri, P. Kapur, & K.C. Saraswat, 3D ICs: A novel chip design for improving deep submicrometer interconnect performance and system-on-chip integration, Proceedings of IEEE, 89, 2001, 602-633.
-
(2001)
Proceedings of IEEE
, vol.89
, pp. 602-633
-
-
Banerjee, K.1
Souri, S.J.2
Kapur, P.3
Saraswat, K.C.4
-
13
-
-
0036866915
-
A power-optimal repeater insertion methodology for global interconnects in nanometer designs
-
K. Banerjee & A. Mehrotra, A power-optimal repeater insertion methodology for global interconnects in nanometer designs, IEEE Transactions on Electron Devices, 49(11), 2002, 2001-2007.
-
(2002)
IEEE Transactions on Electron Devices
, vol.49
, Issue.11
, pp. 2001-2007
-
-
Banerjee, K.1
Mehrotra, A.2
-
14
-
-
15844415671
-
Optimization of throughput performance for low-power VLSI interconnects
-
V.V. Deodhar & J.A. Davis, Optimization of throughput performance for low-power VLSI interconnects, IEEE Transactions on VLSI Systems, 13(3), 2005, 308-318.
-
(2005)
IEEE Transactions on VLSI Systems
, vol.13
, Issue.3
, pp. 308-318
-
-
Deodhar, V.V.1
Davis, J.A.2
-
17
-
-
0036612170
-
High-frequency characterization of on-chip digital interconnects
-
B. Kleveland, X. Qi, L. Madden, T. Furusawa et al., High-frequency characterization of on-chip digital interconnects, IEEE Journal of Solid State Circuits, 37(6), 2002, 716-725.
-
(2002)
IEEE Journal of Solid State Circuits
, vol.37
, Issue.6
, pp. 716-725
-
-
Kleveland, B.1
Qi, X.2
Madden, L.3
Furusawa, T.4
-
18
-
-
0042164618
-
A unified RLC model for high speed on-chip interconnects
-
S.P. Sim, S. Krishnan, D.M. Petranovic, N.D. Arora et al., A unified RLC model for high speed on-chip interconnects, IEEE Transactions on Electron Devices, 50(6), 2003, 1501-1510.
-
(2003)
IEEE Transactions on Electron Devices
, vol.50
, Issue.6
, pp. 1501-1510
-
-
Sim, S.P.1
Krishnan, S.2
Petranovic, D.M.3
Arora, N.D.4
-
19
-
-
0035704577
-
Exploiting the on-chip inductance in high-speed clock distribution networks
-
Y.I. Ismail, E.G. Friedman, & J-L. Neves, Exploiting the on-chip inductance in high-speed clock distribution networks, IEEE Transactions on VLSI Systems, 9(6), 2001, 963-973.
-
(2001)
IEEE Transactions on VLSI Systems
, vol.9
, Issue.6
, pp. 963-973
-
-
Ismail, Y.I.1
Friedman, E.G.2
Neves, J.-L.3
-
20
-
-
0027696514
-
Characterization of the broadband transmission behavior of interconnections on silicon substrates
-
S. Zaage & E. Groteliischen, Characterization of the broadband transmission behavior of interconnections on silicon substrates, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 16(7), 1993, 686-691.
-
(1993)
IEEE Transactions on Components, Hybrids, and Manufacturing Technology
, vol.16
, Issue.7
, pp. 686-691
-
-
Zaage, S.1
Groteliischen, E.2
-
21
-
-
0033363189
-
CAD-oriented equivalent circuit modeling of on-chip interconnects for RF integrated circuits in CMOS technology
-
J. Zheng, Y.-C. Hahm, A. Weisshaar, & V.K. Tripathi, CAD-oriented equivalent circuit modeling of on-chip interconnects for RF integrated circuits in CMOS technology, IEEE Microwave Sym. Digest, MTT-S, 1, 1999, 35-38.
-
(1999)
IEEE Microwave Sym. Digest, MTT-S
, vol.1
, pp. 35-38
-
-
Zheng, J.1
Hahm, Y.-C.2
Weisshaar, A.3
Tripathi, V.K.4
-
22
-
-
0036238958
-
On the frequency-dependent line capacitance and conductance of on-chip interconnects on lossy silicon substrate
-
H. Ymeri, B. Nauwelaers, & K. Maex, On the frequency-dependent line capacitance and conductance of on-chip interconnects on lossy silicon substrate, Microelectronics International, 19(1), 2002, 11-18.
-
(2002)
Microelectronics International
, vol.19
, Issue.1
, pp. 11-18
-
-
Ymeri, H.1
Nauwelaers, B.2
Maex, K.3
-
23
-
-
36949010105
-
-
MOSIS Service for HSPICE models
-
MOSIS Service for HSPICE models. Website: http://www. mosis.org
-
Website
-
-
-
24
-
-
36949027883
-
-
Berkeley Service
-
Berkeley Service. Website: http://www-device.eecs.berkeley.edu/~ptm
-
Website
-
-
-
25
-
-
0033712799
-
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
-
Y. Cao, T. Sata, M. Orshansky, D. Sylvester et al., New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation, Proc. IEEE Conf. on Custom Integrated Circuits, 2000, 201-204.
-
(2000)
Proc. IEEE Conf. on Custom Integrated Circuits
, pp. 201-204
-
-
Cao, Y.1
Sata, T.2
Orshansky, M.3
Sylvester, D.4
-
26
-
-
0030143091
-
Inductance and capacitance analytic formulas for VLSI interconnects
-
N. Delorme, M. Belleville, & J. Chilo, Inductance and capacitance analytic formulas for VLSI interconnects, Electronics Letters, 32(11), 1996, 996-997.
-
(1996)
Electronics Letters
, vol.32
, Issue.11
, pp. 996-997
-
-
Delorme, N.1
Belleville, M.2
Chilo, J.3
-
27
-
-
9644305250
-
Power characteristics of inductive interconnect
-
M.A. El-Moursy & E.G. Friedman, Power characteristics of inductive interconnect, IEEE Transactions on VLSI Systems, 12(12), 2004, 1295-1306.
-
(2004)
IEEE Transactions on VLSI Systems
, vol.12
, Issue.12
, pp. 1295-1306
-
-
El-Moursy, M.A.1
Friedman, E.G.2
|