Lumped versus distributed RC and RLC interconnect impedances

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages 136-139

  Tang, Kevin T ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; FOURIER TRANSFORMS; SPECTRUM ANALYSIS; VLSI CIRCUITS;

CMOS LOGIC GATE; INTERCONNECT IMPEDANCE; ON-CHIP SIGNALS;

LOGIC GATES;

EID: 0034464845     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Analysis of the effects of scaling on interconnect delay in ULSI circuits
2. Optimal interconnection circuits for VLSI
3. Approximation of wiring delay in MOSFET LSI
4. Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas
5. Figures of merit to characterize the importance of on-chip inductance
6. Inductance in VLSI interconnection modeling
7. Inductance on silicon for sub-micron CMOS VLSI