CA-RAM: A high-performance memory substrate for search-intensive applications

ISPASS 2007: IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2007, Pages 230-241

  Cho, Sangyeun ^a   Martin, Joel R ^a   Xu, Ruibin ^a   Hammoud, Mohammad H ^a   Melhem, Rami ^a  

^a University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTENT ADDRESSABLE MEMORY (CAM); CONTENT ADDRESSABLE RANDOM ACCESS MEMORY (CA-RAM);

COMPUTER ARCHITECTURE; DATA MINING; DATABASE SYSTEMS; INTERNET PROTOCOLS; ROUTERS; SPEECH RECOGNITION; STORAGE ALLOCATION (COMPUTER);

RANDOM ACCESS STORAGE;

EID: 36949011387     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2007.363753     Document Type: Conference Paper

References (32)

1. ACT-R cognitive architecture, http://act-r.psy.cmu.edu.
2. S. Borkar et al. "Platform 2015: Intel Processor and Platform Evolution for the Next Decade," Platform 2015 White Paper, Intel Corp., Mar. 2005.
3. R. Brodersen. "Low Voltage Design for Portable Systems," Proc. Int'l Solid State Circuits Conf., pp. 566-570, Feb. 2002.
4. D. Burger and J. R. Goodman. "Billion-Transistor Architectures: There and Back Again." IEEE Computer, 37(3):22-28, Mar. 2004.
5. The CMU Sphinx Speech Recognition Engine, http://www.speech.ce.crau.edu/ sphinx/.
6. P. Dubey. "Recognition, Mining and Synthesis Moves Computers to the Era of Tera," Platfoan 2015 White Paper, Intel, Mar. 2005.
7. S. Hanzawa et al. "A Large-Scale and Low-Power CAM Architecture Featuring a One-Hot-Spot Block Code for IP-Address Lookup in a Network Router," IEEE J. Solid-State Circuits, 40(4):853-861, Apr. 2005.
8. J. L. Hennessy and D. A. Patterson. Computer Architecture A Quantitative Approach, 3rd Ed., Morgan Kaufmann, 2003.
9. D. Huggins-Daines et al. "PocketSphinx: A Free, Real-Time Continuous Speech Recognition System, for Hand-Held Devices," Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing, pp. I185-1-188, May 2006.
10. G. Huston. "Analyzing the Internet's BGP Routing Table," The Internet Protocol J., Vol.4, 2001.
11. N. P. Jouppi. "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. Int'l Symp. Computer Architecture, pp. 364-373, June 1990.
12. M. Karlsson et al. "A Prefetching Technique for Irregular Accesses to Linked Data Structures," Proc. Int'l Symp. High-Performance Computer Architecture, pp. 206-217, Jan. 2000.
13. G. Kasai et al. "200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits Ternary CAM with New Charge Injection Match Detect Circuits and Bank Selection Scheme," Proc. IEEE Custom Integrated Circuits Conf., pp. 387-390, Sept. 2003.
14. D. E. Knuth. The Art of Computer Programming, Vol. 3 (Sorting and Searching), Addison-Wesley, 1973.
15. T. Kohonen. Confent-Addressable Memories, Springer-Verlag, 1980.
16. C.-S. Lin, J.-C. Chang, and B.-D. Liu. "A Low-Power Precomputation-Based Fully Parallel Con tent- Addressable Memory," IEEE J. Solid-State Circuits, 38(4): 654-662, Apr. 2003.
17. E. Lin. "A First Generation Hardware Reference Model for a Speech Recognition Engine," MS Thesis, School of Electrical and Computer Eng., Carnegie Mellon Univ., May 2003.
18. H.Liu. "Reducing Routing Table Size Using Ternary-CAM," Proc. Symp. High-Performance Interconnects, Aug. 2001.
19. Micron Technology. DRAM products. http ://www.micron.com/product s/dram/.
20. F. Morishita et al. "A 312-MHz 16-Mb Random-Cycle Embedded DRAM Macro with a Power-Down Data Retention Mode for Mobile Applications," IEEE J. Solid-State Circuits, 40(1):204-212, Jan. 2005.
21. M. Motomura et al. "A 1.2-Million Transistor, 33-MHz, 20-b Dictionary Search Processor (DISP) ULSI with a 160-kb CAM," IEEE J. Solid-State Circuits, 25(5):1158-1165, Oct. 1990.
22. G. Narlikar and F. Zane. "Performance Modeling for Fast IP Lookups," Proc. ACM SIGMETRICS Int'l Conf. Measurement and Modeling of Computer Systems, pp. 1-12, June 2001.
23. H. Noda et al. "A Cost-Efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture," Proc. Int'l Symp. VLSI Circuits, June 2003.
24. H. Noda et al. "A Cost-Efficient High-Performance Dynamic TCAM With Pipelined Hierarchical Searching and Shift Redundancy Architecture," IEEE J. Solid-State Circuits, 40(1):245-253, Jan. 2005.
25. K. Pagiamtzis and A. Sheikholeslami. "Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey," IEEE J. Solid-State Circuits, 41(3):712-727, Mar. 2006.
26. Y. Rekhter and T. Li. "An Architecture for IP Address Allocation with. CIDR," RFC 1518, 1993.
27. Routinglnf. Service, http://www.ripe.net/ris/. 2006.
28. K. J. Schultz and P. G. Gulak. "Fully Parallel Integrated CAM/RAM Using Reclassification to Enable Large Capacities," IEEE J. Solid-State Circuits, 31(5):689-699, May 1996.
29. D. Shah and P. Gupta. "Fast Updating Algorithms for TCAMs," IEEE Micro, 21(1):36-47, Jan./Feb. 2001.
30. S. Vakulenko. Hash Function Efficiency. http ://www.vak.ru/doku. php/proj/hash/efficiency-en.
31. T. Yamagata et al. "A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure," IEEE J. Solid-State Circuits, 27(12):1927-1933, Dec. 1992.
32. F. Zane, G. Narlikar, and A. Basu. "CoolCAMs: Power-Efficient TCAMs for Forwarding Engines," Proc. IEEE Conf. Computer Communications, pp. 42-52, Apr. 2003.