Reducing routing table size using ternary-CAM

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects

Volumn 2001-January, Issue , 2001, Pages 69-73

  Liu, Huan ^a  

^a Stanford University   (United States)

Author keywords

Associative memory; CADCAM; Compaction; Computer aided manufacturing; Cost function; Delay; Energy consumption; Internet; Routing protocols; Throughput

Indexed keywords

ASSOCIATIVE PROCESSING; ASSOCIATIVE STORAGE; COMPACTION; COMPUTER AIDED MANUFACTURING; COST FUNCTIONS; ENERGY UTILIZATION; INTERNET; INTERNET PROTOCOLS; LOGIC GATES; MEMORY ARCHITECTURE; POWER MANAGEMENT (TELECOMMUNICATION); ROUTERS; ROUTING PROTOCOLS; THROUGHPUT;

ASSOCIATIVE MEMORY; CADCAM; COMPACT ROUTING TABLES; DELAY; HIGH-SPEED ROUTERS; INCREMENTAL UPDATES; TERNARY CONTENT ADDRESSABLE MEMORY; THERMAL DISSIPATION;

TERNARY CONTENT ADRESSABLE MEMORY;

EID: 84950121248     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HIS.2001.946696     Document Type: Conference Paper

References (20)

1. Y. Rekhter, T. Li, "An Architecture for IP Address Allocation with CIDR," RFC 1518, 1993
2. S. Nilsson, G. Karlsson, "IP-address lookup using LC-tries," IEEE Journal on Selected Areas in Communications, vol. 17, no. 6, pp. 1083-1092, 1999.
3. P. Gupta, B. Prabhakar and S. Boyd, "Near-Optimal Routing Lookups with Bounded Worst Case Performance," Proc. Infocom, vol. 3, pp 1184-92, March 2000, Tel Aviv, Israel.
4. D. Shah and P. Gupta, "Fast Updates on Ternary-CAMs for Packet Lookups and Classification," Proc. Hot Interconnects VIII, August 2000, Stanford.
5. G. Bollano, S. Claretto, E. Filippi, A. Torielli and M. Turolla, "Merging Hardware and Software: Intellectual Property Cores for Internet Applications," Proc. IEEE CICC, 2000, Orlando, Florida.
6. P. Gupta, S. Lin and N. McKeown, "Routing Lookups in Hardware at Memory Access Speeds," Proc. Infocom. April 98, San Francisco
7. T. Hayashi and T. Miyazaki, "High-Speed Table Lookup Engine for IPv6 Longest Prefix Match," Proc. Globecom, 1999, vol. 2, pp 1576-1581
8. Merit Networks, Inc., http://www.merit.edu/ipma
9. M. Waldvogel, G. Varghese, J. Turner, B. Plattner, "Scalable High-Speed IP Routing Lookups," Proc. ACM SIGCOMM 1997, pp. 25-36, Cannes, France.
10. A. Brodnik, S. Carlsson, M. Degermark, S. Pink, "Small Forwarding Tables for Fast Routing Lookups," Proc. ACM SIGCOMM 1997, pp. 3-14, Cannes, France.
11. V. Srinivasan and G. Varghese, "Fast Address Lookups Using Controlled Prefix Expansion," ACM Transactions on Computer Systems, Vol. 17, no. 1, pp. 1-40, Oct. 1999
12. Netlogic microsystems, "Ternary Synchronous Content Addressable Memory (IPCAM)," http://www.netlogicmicro.com/pdf/NL82721.pdf
13. S. Nilsson and G. Karlsson, "IP-address Lookup using LC-tries," IEEE Journal on Selected Areas in Communications, Vol. 17, no. 6, pp. 1083-92, 1999.
14. T.B. Pei and C. Zukowski, "VLSI Implementation of Routing Tables: Tries and CAMs," Proc. Infocom 91
15. A. McAuley and P. Francis, "Fast Routing Table Lookup Using CAMs", Proc. Infocom 93, Vol. 3, pp. 1382-91, Mar. 1993.
16. M. Kobayashi, T. Murase and A. Kuriyama, "A Longest Prefix Match Search Engine for Multi-Gigabit IP Processing", Proc. ICC 2000, June 2000.
17. R.K. Brayton, et al., Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Boston, MA., 1984
18. I. Hsiao and C.W. Jen, "A New Hardware Design and FPGA Implementation for Internet Routing towards IP over WDM and Terabit Routers", Proc. IEEE Symposium on Circuits and Systems, Vol. 1, pp. 387-390, 2000
19. T.C. Chiueh and P. Pradhan, "Cache Memory Design for Network Processors," Proc. High Performance Computer Architecture, pp. 409-418, 1999.
20. C. Labovitz, G.R. Malan and F. Jahanian, "Internet Routing Instability," The IEEE/ACM Transactions on Networking, Vol. 6, no. 5, pp. 515-528, 1999.