A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 204-210

  Morishita, Fukashi ^a   Hayashi, Isamu ^a   Matsuoka, Hideto ^a   Takahashi, Kazuhiro ^b   Shigeta, Kuniyasu ^b   Gyohten, Takayuki ^a   Niiro, Mitsutaka ^a   Noda, Hideyuki ^a   Okamoto, Mako ^c   Hachisuka, Atsushi ^a   Amo, Atsushi ^a   Shinkawata, Hiroki ^a   Kasaoka, Tatsuo ^a   Dosaka, Katsumi ^a   Arimoto, Kazutami ^a   Fujishima, Kazuyasu ^a   Anami, Kenji ^a   Yoshihara, Tsutomu ^d  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Design   (Japan)

^c Daioh Electric Corp   (Japan)

^d WASEDA UNIVERSITY   (Japan)

Author keywords

CMOS memory integrated circuits; Embedded DRAM; Mobile applications; System on chip

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; MOBILE TELECOMMUNICATION SYSTEMS; SIGNAL PROCESSING; SYNCHRONIZATION; THIN FILM TRANSISTORS;

EMBEDDED DRAM; MOBILE APPLICATIONS; NEGATIVE EDGE TRANSMISSION (NET); SYSTEM-ON-CHIP;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 19944429374     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.837986     Document Type: Conference Paper

References (8)

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