A Cost-efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 83-84

  Noda, Hideyuki ^a   Inoue, Kazunari ^b   Mattausch, Hans Juergen ^c   Koide, Tetsushi ^c   Arimoto, Kazutami ^a  

^a ULSI Development Center   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c HIROSHIMA UNIVERSITY   (Japan)

Author keywords

CMOS; Complementary; Dynamic; Network; Planar; Refresh; Ternary CAM

Indexed keywords

CAPACITORS; COMPUTER AIDED MANUFACTURING; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COST EFFECTIVENESS; DYNAMIC RANDOM ACCESS STORAGE;

MATCH LINES (ML);

CMOS INTEGRATED CIRCUITS;

EID: 0141538242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Pamkai Gupta and Nick McKeown, "Algorithms for Packet Classification," p.24 IEEE Network, March/April 2001