-
1
-
-
84954157901
-
Present and future trend of electron device technology in flat panel display
-
T. Uchida, "Present and future trend of electron device technology in flat panel display," in IEDM Tech. Dig., 1991, pp. 5-10.
-
(1991)
IEDM Tech. Dig
, pp. 5-10
-
-
Uchida, T.1
-
2
-
-
0036930458
-
Needs and solutions of future flat panel display for information technology industry
-
K. Chung, M.-P. Hong, C.-W. Kim, and I. Kang, "Needs and solutions of future flat panel display for information technology industry," in IEDM Tech. Dig., 2002, pp. 385-388.
-
(2002)
IEDM Tech. Dig
, pp. 385-388
-
-
Chung, K.1
Hong, M.-P.2
Kim, C.-W.3
Kang, I.4
-
3
-
-
0025671540
-
A half-micron SRAM cell using a double-gated self-aligned polysilicon pMOS thin film transistor (TFT) load
-
A. O. Adan, K. Suzuki, H. Shibayama, and R. Miyake, "A half-micron SRAM cell using a double-gated self-aligned polysilicon pMOS thin film transistor (TFT) load," in VLSI Symp. Tech. Dig., 1990, pp. 19-20.
-
(1990)
VLSI Symp. Tech. Dig
, pp. 19-20
-
-
Adan, A.O.1
Suzuki, K.2
Shibayama, H.3
Miyake, R.4
-
4
-
-
0031644053
-
A novel pillar DRAM cell for 4 Git and beyond
-
H. J. Cho, F. Nemati, P. B. Griffin, and J. D. Plummer, "A novel pillar DRAM cell for 4 Git and beyond," in VLSI Symp. Tech. Dig., 1998, pp. 38-39.
-
(1998)
VLSI Symp. Tech. Dig
, pp. 38-39
-
-
Cho, H.J.1
Nemati, F.2
Griffin, P.B.3
Plummer, J.D.4
-
5
-
-
0034452606
-
A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structure
-
K. Ohgata, Y. Mishima, and N. Sasaki, "A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structure," in IEDM Tech. Dig., 2000, pp. 205-208.
-
(2000)
IEDM Tech. Dig
, pp. 205-208
-
-
Ohgata, K.1
Mishima, Y.2
Sasaki, N.3
-
6
-
-
29244445531
-
A new polysilicon CMOS self-aligned double-gate TFT technology
-
Dec
-
Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, "A new polysilicon CMOS self-aligned double-gate TFT technology," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 2629-2633, Dec. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.2
, pp. 2629-2633
-
-
Xiong, Z.1
Liu, H.2
Zhu, C.3
Sin, J.K.O.4
-
7
-
-
0033169527
-
Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAMs
-
Aug
-
S. Miyamoto, S. Maegawa, S. Maeda, T. Ipposhi, H. Kuriyama, T. Nishimura, and N. Tsubouchi, "Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAMs," IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1693-1698, Aug. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.8
, pp. 1693-1698
-
-
Miyamoto, S.1
Maegawa, S.2
Maeda, S.3
Ipposhi, T.4
Kuriyama, H.5
Nishimura, T.6
Tsubouchi, N.7
-
8
-
-
33646263586
-
High-performance poly-silicon TFTs using HfO2 gate dielectric
-
May
-
C.-P. Lin, B.-Y Tsw, M.-J. Yang, R.-H. Huang, and C.-H. Chien, "High-performance poly-silicon TFTs using HfO2 gate dielectric," IEEE Electron Device Lett., vol. 27, no. 5, pp. 360-363, May 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.5
, pp. 360-363
-
-
Lin, C.-P.1
Tsw, B.-Y.2
Yang, M.-J.3
Huang, R.-H.4
Chien, C.-H.5
-
9
-
-
33947375692
-
Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels
-
Oct
-
Y.-C. Wu, T.-C. Chang, P.-T. Liu, C.-S. Chen, C.-H. Tu, H.-W. Zan, Y.-H. Tai, and C.-Y. Chang, "Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2343-2346, Oct. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.10
, pp. 2343-2346
-
-
Wu, Y.-C.1
Chang, T.-C.2
Liu, P.-T.3
Chen, C.-S.4
Tu, C.-H.5
Zan, H.-W.6
Tai, Y.-H.7
Chang, C.-Y.8
-
10
-
-
28344443268
-
-
Y.-C. Wu, T.-C. Chang, P.-T. Liu, Y.-C. Wu, C.-W. Chou, C.-H. Tu, J.-C. Lou, and C.-Y. Chang, Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization, Appl. Phys. Lett., 87, pp. 143 504-1-143 504-3, 2005.
-
Y.-C. Wu, T.-C. Chang, P.-T. Liu, Y.-C. Wu, C.-W. Chou, C.-H. Tu, J.-C. Lou, and C.-Y. Chang, "Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization," Appl. Phys. Lett., vol. 87, pp. 143 504-1-143 504-3, 2005.
-
-
-
-
11
-
-
33947244195
-
Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channel
-
Oct
-
H.-C. Lin, M.-H. Lee, C.-J. Su, and S.-W. Shen, "Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channel," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2471-2477, Oct. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.10
, pp. 2471-2477
-
-
Lin, H.-C.1
Lee, M.-H.2
Su, C.-J.3
Shen, S.-W.4
-
12
-
-
34247853204
-
Operations of poly-Si nanowire thin-film transistor with a multiple-gated configuration
-
May
-
C.-J. Su, H.-C. Lin, H.-H. Tsai, H.-H. Hsu, T.-M. Wang, T.-Y. Huang, and W.-X. Ni, "Operations of poly-Si nanowire thin-film transistor with a multiple-gated configuration," Nanotechnology, vol. 18, no. 21, p. 215 205, May 2007.
-
(2007)
Nanotechnology
, vol.18
, Issue.21
, pp. 215-205
-
-
Su, C.-J.1
Lin, H.-C.2
Tsai, H.-H.3
Hsu, H.-H.4
Wang, T.-M.5
Huang, T.-Y.6
Ni, W.-X.7
-
13
-
-
2342652355
-
Triple-gate metal-oxide effect transistors fabricated with interference lithography
-
M. C. Lemme, C. Moormann, H. Lerch, M. Moller, B. Vratzor, and H. Kurz, "Triple-gate metal-oxide effect transistors fabricated with interference lithography," Nanotechnology, vol. 15, no. 15, pp. S208-S210, 2004.
-
(2004)
Nanotechnology
, vol.15
, Issue.15
-
-
Lemme, M.C.1
Moormann, C.2
Lerch, H.3
Moller, M.4
Vratzor, B.5
Kurz, H.6
-
14
-
-
21044447633
-
On the feasibility of nanoscale triple-gate CMOS transistors
-
Jun
-
J.-W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple-gate CMOS transistors," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.6
, pp. 1159-1164
-
-
Yang, J.-W.1
Fossum, J.G.2
-
15
-
-
0034321619
-
An analytical model for current-voltage characteristics of a small-geometry poly-Si thin-film transistor
-
Nov
-
S. Chopra and R. S. Gupta, "An analytical model for current-voltage characteristics of a small-geometry poly-Si thin-film transistor," Semicond. Sci. Technol., vol. 15, no. 11, pp. 1065-1070, Nov. 2000.
-
(2000)
Semicond. Sci. Technol
, vol.15
, Issue.11
, pp. 1065-1070
-
-
Chopra, S.1
Gupta, R.S.2
-
16
-
-
0024894432
-
Drastically improved performance in poly-Si TFTs with channel dimensions comparable to grain size
-
N. Yamauchi, J. J. Hajjar, and R. Reif, "Drastically improved performance in poly-Si TFTs with channel dimensions comparable to grain size," in IEDM Tech. Dig., 1989, pp. 353-356.
-
(1989)
IEDM Tech. Dig
, pp. 353-356
-
-
Yamauchi, N.1
Hajjar, J.J.2
Reif, R.3
-
17
-
-
0035308163
-
On-current modeling of large-grain polycrystalline silicon thin-film transistors
-
Apr
-
F. V. Farmakis, J. Brini, G. Kamarinos, C. T. Angelis, C. A. Dimitriadis, and M. Miyasaka, "On-current modeling of large-grain polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 701-706, Apr. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.4
, pp. 701-706
-
-
Farmakis, F.V.1
Brini, J.2
Kamarinos, G.3
Angelis, C.T.4
Dimitriadis, C.A.5
Miyasaka, M.6
|