Adding synchronous and LSSD modes to asynchronous circuits

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2002, Pages 161-169

  Van Berkel, Kees ^a,b   Peeters, Ad ^a   Beest, Frank Te ^c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DELAY CIRCUITS; TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITS; CIRCUIT DELAYS; CIRCUIT OPERATION; DESIGN FOR TEST; DESIGN-FOR-TESTABILITY; DYNAMIC CIRCUITS; MODE OF OPERATIONS; SCAN MODE; TEST PATTERN GENERATIONS;

DESIGN FOR TESTABILITY;

EID: 77957962915     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

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