Design of on-chip and off-chip interfaces for a GALS NoC architecture

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn 2006, Issue , 2006, Pages 174-183

  Beigne E ^a   Vivet, P ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS MACHINERY; INTERFACES (COMPUTER); RAPID PROTOTYPING; SYNCHRONOUS MACHINERY;

ASYNCHRONOUS NOC DOMAINS; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS); MULTI-CLOCK SYNCHRONIZATION; OPEN-PLATFORM PROTOTYPING;

INTEGRATED CIRCUIT LAYOUT;

EID: 33749613794     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2006.16     Document Type: Conference Paper

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