Improving DPA security by using globally-asynchronous locally-synchronous systems

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 407-410

  Gürkaynak, Frank ^a   Oetiker, Stephan ^a   Kaeslin, Hubert ^a   Felber, Norbert ^a   Fichtner, Wolfgang ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; CMOS INTEGRATED CIRCUITS; COMPUTER CRIME; COMPUTER HARDWARE; CORRELATION METHODS; SECURITY OF DATA;

DIFFERENTIAL POWER ANALYSIS (DPA); GLOBALLY-ASYCHRONOUS LOCALLY-SYNCHRONOUS (GALS) SYSTEMS; SIDE CHANNEL ANALYSIS ATTACKS;

CRYPTOGRAPHY;

EID: 33749167688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541646     Document Type: Conference Paper

References (10)

1. D. M. Chapiro. Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Stanford University, October 1984.
2. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems, E80-D(3):315-325, March 1997.
3. J. J. A. Fournier, S. Moore, H. Li, R. Mullins, and G. Taylor. Security evaluation of asynchronous circuits. In CUES '03: Workshop on Cryptographic Hardware and Embedded Systems, pages 137-151. Springer-Verlag, 2004.
4. P. Kocher. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. Lecture Notes in Computer Science, 1109:104-113, 1996.
5. P. Kocher, J. Jaffe, and B. Jun. Differential power analysis. Lecture Notes in Computer Science, 1666:388-397, 1999.
6. J. Muttersbach. Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems, PhD thesis, ETH, Zurich, 2001.
7. S. Oetiker, F. K. Gürkaynak, T. Villiger, H. Kaeslin, N. Felber, and W. Fichtner. Design flow for a 3-million transistor GALS test chip. In Handouts of the Third Asynchronous Circuit Design Workshop, ACiD 2003, Heraklion, Greece, January 2003.
8. National Institute of Standards and Technology (NIST). Advanced Encryption Standard (AES). FIPS Publication, 197, 2001.
9. N. Pramstaller, F. K. Gürkaynak, S. Haene, H Kaeslin, N. Felber, and W. Fichtner. DPA Resistant AES Crypto-Chip Design. In Proc. European Solid-State Circuits Conference (ESSCIRC), pages 307-310. IEEE Press, 2004.
10. S. B. Örs, F. K. Gürkaynak, E. Oswald, and B. Preneel. Power-Analysis Attacks on an ASIC AES Implementation. In Proc. of International Conference on Information Technology (ITCC), pages 546-552, April 2004.