Unified microprocessor core storage

2007 Computing Frontiers, Conference Proceedings

Volumn , Issue , 2007, Pages 23-34

  Meixner, Albert ^a   Sorin, Daniel J ^b  

^a Duke University   (United States)

^b Duke University   (United States)

Author keywords

Microarchitecture; Power efficiency; Resource allocation; Unified caching

Indexed keywords

MICROARCHITECTURE; POWER EFFICIENCY; UNIFIED CACHING;

ENERGY UTILIZATION; RESOURCE ALLOCATION; STORAGE ALLOCATION (COMPUTER);

MICROPROCESSOR CHIPS;

EID: 35348844113     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1242531.1242538     Document Type: Conference Paper

References (39)

1. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. In Proc. of 36th Annual Int 'I Symposium on Microarchitecture, Dec. 2003.
2. D. H. Albonesi. Dynamic IPC/Clock Rate Optimization. In Proc. of the 25th Annual International Symposium on Computer Architecture, pages 282-292, June 1998.
3. D. H. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. In Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 248-259, Nov. 1999.
4. T. Austin, E. Larson, and D. Ernst. SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer, 35(2):59-67, Feb. 2002.
5. R. Balasubramonian et al. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. In Proc. of the 33rd Annual Int'l Symposium on Microarchitecture, pages 245-257, Dec. 2000.
6. E. Brekelbaum et al. Hierarchical Scheduling Windows. In Proc. of the 35th Annual International Symposium on Microarchitecture, pages 27-36, Nov. 2002.
7. A. Buyuktosunoglu et al. A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors. In Proc. of the 11th Great Lakes Symposium on VLSI, pages 73-78, 2001.
8. J.-L. Cruz et al. Multiple-Banked Register File Architectures. In Proc. of 27th Annual Int'l Symposium on Computer Architecture, pages 316-325, June 2000.
9. S. Dutta, K. J. O'Connor, and A. Wolfe. High-Performance Crossbar Interconnect for a VLIW Video Signal Processor. In IEEE International ASIC Conference, pages 45-50, Sept. 1996.
10. D. Folegnani and A. González. Energy-Effective Issue Logic. In Proc. of 28th Annual International Symposium on Computer Architecture, pages 230-239, July 2001.
11. C. Gniady, B. Falsafi, and T. Vijaykumar. Is SC + ILP = RC? In Proc. of the 26th Annual International Symposium on Computer Architecture, pages 162-171, May 1999.
12. E. G. Hallnor and S. K. Reinhardt. A Fully Associative Software-Managed Cache Design. In Proc. of 27th Annual International Symposium on Computer Architecture, pages 107-116, June 2000.
13. A. Iyer and D. Marculescu. Power Aware Microarchitecture Resource Scaling. In Proc. of Design, Automation and Test in Europe Conference, Mar. 2001.
14. D. J. Jimenez, S. W. Keckler, and C. Lin. The Impact of Delay on the Design of Branch Predictors. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2000.
15. N. P. Jouppi and S. J. Wilton. An Enhanced Access and Cycle Time Model for On-Chip Caches. DEC WRL Research Report 93/5, July 1994.
16. S. Kaxiras, Z. Hu, and M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Proc. of the 28th Annual International Symposium on Computer Architecture, July 2001.
17. J. Kin, M. Gupta, and W. H. Mangione-Smith. The Filter Cache: An Energy Efficient Memory Structure. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 184-193, Dec. 1997.
18. K. Krewel. Alpha EV7 Processor: A High-Performanee Tradition Continues. Microprocessor Report, April 2005.
19. E. Kursun et al. An Evaluation of Deeply Decoupled Cores. Journal of Instruction-Level Parallelism, 8:1-20, Apr. 2006.
20. A. R. Lebeck et al. A Large, Fast Instruction Window for Tolerating Cache Misses. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 59-70, May 2002.
21. L. Li et al. CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. In DSD '03: Proc. of the Euromicro Symposium on Digital Systems Design, page 41, 2003.
22. S. Manne, A. Klauser, and D. Grunwald. Pipeline Gating: Speculation Control for Energy Reduction. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 132-141, June 1998.
23. D. W. Oehmke et al. How to Fake 1000 Registers. In Proc. of the 38th Annual International Symposium on Microarchitecture, pages 7-18, Nov. 2005.
24. S. Palacharla and J. E. Smith. Complexity-Effective Superscalar Processors. In Proceedings of the 24th Annual International Symposium on Computer Architecture, pages 206-218, June 1997.
25. D. Ponomarev, G. Kucuk, and K. Ghose. Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources. In Proc. of the 34rd Annual International Symposium on Microarchitecture, pages 90-101, Dec. 2001.
26. M. Powell et al. Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping. In Proceedings of the 34rd Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2001.
27. M. K. Qureshi, D. Thompson, and Y. N. Part. The V-Way Cache: Demand-Based Associativity via Global Replacement. In Proc. of 32nd Annual Int'l Symposium on Computer Architecture, pages 544-555, June 2005.
28. P. Ranganathan, V. S. Pai, and S. V. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In Proc. of the Ninth ACM Symposium on Parallel Algorithms and Architectures, pages 199-210, June 1997.
29. G. Reinman, T. Austin, and B. Calder. A Scalable Front-End Architecture for Fast Instruction Delivery. In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 234-245, May 1999.
30. J. A. Rivers et al. On High-Bandwidth Data Cache Design for Multi-Issue Processors. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture, pages 46-56, Dec. 1997.
31. R. M. Russell. The Cray-1 Computer System. Communications of the ACM, 21(1):63-72, Jan. 1978.
32. T. Sherwood et al. Automatically Characterizing Large Scale Program Behavior. In Proc. of the Tenth Int'l Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2002.
33. K. Skadron et al. Temperature-aware microarchitecture. In Proc. of the 30th Annual International Symposium on Computer Architecture, pages 2-13, June 2003.
34. G. S. Sohi and S. Vajapeyam. Instruction Issue Logic for High-Performance Interruptable Pipelined Processors. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 27-34, June 1987.
35. J. A. Swensen and Y. N. Patt. Hierarchical Registers for Scientific Computers. In Proc. of the 1988 Int'l Conf. on Supercomputing, pages 346-354, July 1988.
36. H. Wang, L.-S. Peh, and S. Malik. A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 1238-1243, 2005.
37. S.-H. Yang et al. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep Submicron High-Performance Caches. In Proc. of the Seventh IEEE Symposium on High-Performance Computer Architecture, pages 147-157, Jan. 2001.
38. S.-H. Yang et al. Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. In Proceedings of the Eighth IEEE Symposium on High-Performance Computer Architecture, Jan. 2002.
39. J. Zalamea et al. Two-Level Hierarchical Register File Organization for VLIW Processors. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, pages 137-146, Dec. 2000.