The V-Way cache: Demand-based associativity via global replacement

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2005, Pages 544-555

  Qureshi, Moinuddin K ^a   Thompson, David ^a   Patt, Yale N ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY LATENCY; SET-ASSOCIATIVE CACHES;

BUFFER STORAGE; INTELLIGENT AGENTS; SET THEORY;

PROGRAM PROCESSORS;

EID: 27644555246     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2005.52     Document Type: Conference Paper

References (19)

1. A. Agarwal, J. Hennessy, and M. Horowitz. cache performance of operating systems and multiprogramming. In ACM Transactions on Computer Systems, 6, pages 393-431, November 1988.
2. L. A. Belady. A study of replacement algorithms for a virtual-storage computer. In IBM Systems journal, pages 78-101, 1966.
3. B. Calder, D. G, and J. Emer. Predictive sequential associative cache. In Proceedings of the Second IEEE International Symposium on High Performance Computer Architecture, pages 244-253, 1996.
4. Z. Chishti, M. D. Powell, and T. N. Vijayhimar. Distance associativity for high-performance energy-efficient non-uniform cache architectures. In Proceedings of the 36th Annual ACM/IEEE International Symposium on Microarchitecture, pages 55-66, 2003.
5. F. J. Corbato. A paging experiment with the multics system MIT project MAC Report MAC-M-384, May 1968.
6. Digital Equipment Corporation, Hudson, MA. Digital Semiconductor 21164 Alpha Microprocessor Product Brief, Mar. 1997. Technical Document EC-QP97D-TE.
7. E. G. Hallnor and S. K. Reinhardt. A fully associative software-managed cache design. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 107-116, 2000.
8. T. L. Jhonson. Run-lime adaptive cache management. PhD thesis. University of Illinois, Urbana, IL, May 1998.
9. N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 364-373, 1990.
10. M. Kharbutli, K. Irwin, Y. Solihin, and J. Lee. Using prime numbers for cache indexing to eliminate confict misses. In Proceedings of the Tenth IEEE International Symposium on High Performance Computer Architecture, pages 288-299, 2004.
11. C. Kim, B. D., and S. Keckler. An adaptive, nonuniform cache structure for wiredelay dominated onchip caches, pages 211-222, 2002.
12. A. R. Lebeck. Cache conscious programming in undergraduate computer science. In ACM SIGCSE Technical Symposium on Computer Science Education (SIGCSE 99), 1999.
13. J.-K. Peir, Y. Lee, and W. W. Hsu. Capturing dynamic memory reference behavior with adaptive cache topology. In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 134-143, 1998
14. T. R. Puzak. Analysis of cache replacement algorithms. PhD thesis, Univ. of Mass., ECE Dept., Amherst, MA., 1985.
15. A. Seznec. A case for two-way skewed-associative caches. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 169-178, 1993.
16. A. J. Smith. Sequentiality and prefetching in database systems. ACM Transaction on Database Systems, 3(3):223-247, September 1978.
17. A. J. Smith. Cache memories. Computing Surveys, 14(4), 1982.
18. D. Weiss, J. J. Wuu, and V. Chin. The on-chip 3-mb subarray-based third-level cache on an itanium microprocessor. In IEEE journal of solid state circuits, pages 1523-1529, Nov. 2002.
19. S. J. E. Wilton and N. P. Jouppi. Cacti: an enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31:677-688, May 1996.