An efficient design of residue to binary converter for four moduli set (2n - 1, 2n + 1, 22 n - 2, 22 n + 1 - 3) based on new CRT II

Information Sciences

Volumn 178, Issue 1, 2008, Pages 264-279

  Zhang, Wei ^a   Siy, Pepe ^a  

^a Wayne State University   (United States)

Author keywords

New Chinese Remainder Theorem 2 (New CRT II); Residue number system (RNS); Residue to binary converter

Indexed keywords

COMPUTATIONAL COMPLEXITY; SYSTEMS ANALYSIS; THEOREM PROVING;

NEW CHINESE REMAINDER THEOREM 2 (NEW CRT II); RESIDUE NUMBER SYSTEM (RNS); RESIDUE TO BINARY CONVERTER;

BINARY SEQUENCES;

EID: 34948884118     PISSN: 00200255     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.ins.2007.05.040     Document Type: Article

References (27)

1. Al-Radadi E., and Siy P. Four-moduli set simplifies the residue to binary converters based on CRT II. Computers and Mathematics with Applications 44 12 (2002) 1581-1587
2. Ananda Mohan P.V., and Poornaiah D.V. Novel RNS to binary converters. 1991 IEEE International Symposium on Circuits and Systems, Part 3 (of 5), Jun 11-14 (1991), IEEE, Piscataway, NJ, USA, Singapore, Singapore pp. 1541-1544
3. Baker R.J. CMOS Circuit Design, Layout, and Simulation (2004), IEEE Press
4. Bayoumi M.A., Jullien G.A., and Miller W.C. A VLSI implementation of residue adder. IEEE Transactions on Circuits and Systems 34 3 (1987) 284-288
5. n + 1 + 1). IEEE Symposium on Computer Arithmetic (1999) 168-175
6. 2 n + 1) based on the new Chinese remainder theorem. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 50 10 (2003) 1296-1303
7. Cao B., Srikanthan T., and Chang C. Design of a high speed reverse converter for a new 4-moduli set residue number system. Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 25-28 (2003), Institute of Electrical and Electronics Engineers Inc., Bangkok, Thailand 520-523
8. Cao B., Srikanthan T., and Chang C. Design of residue-to-binary converter for a new 5-moduli superset residue number system. 2004 IEEE International Symposium on Circuits and Systems, 23-26 May (2004), IEEE, Vancouver, BC, Canada 841-844
9. Cardarilli G.C., Re M., and Lojacono R. RNS-to-binary conversion for efficient VLSI implementation. IEEE Transactions of Circuits and Systems II 45 (1998) 667-669
10. h + 1}. Information Sciences 22 176 (2006) 3426-3430
11. Hiasat A.A. New design for a sign detector and a residue to binary converter. Proceedings of the Tenth IASTED International Conference. Applied Informatics, 10-12 February (1992), Acta Press, Innsbruck, Austria 110-113
12. Hiasat A.A. An arithmetic residue to binary conversion technique. Integration, the VLSI Journal 36 1-2 (2003) 13-25
13. Kang D., Ryu J., and Cho J. A higher-speed architecture for residue to binary number system conversion. Proceedings of Ninth International Symposium on Integrated Circuits, Devices and Systems, 3-5 September (2001), Nanyang Technological University, Singapore 246-249
14. J. Mathew, D. Radhakrishnan, T. Srikanthan, Residue-to-binary arithmetic converter for moduli set, in: Proceedings of the IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing (NSIP'99), 20-23 June 1999, Bogazici University, Antalaya, Turkey, 1999, pp. 190-193.
15. Mathew J., Radhakrishnan D., and Srikanthan T. Fast residue-to-binary converter architectures. 42nd Midwest Symposium on Circuits and Systems, 8-11 August (2000), IEEE, Las Cruces, NM, USA pp. 1090-1093
16. Piestrak S.J. A high speed realization of a residue to binary system converter. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 42 10 (1995) 661-663
17. Sheu M.-H., Lin S., Chen C., and Yang S. An efficient VLSI design for a residue to binary converter for general balance moduli. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 51 3 (2004) 152-155
18. Soderstrand M.A., Jenkins W.K., and Jullien F.T.G. Residue Number System Arithmetic:Modern Applications in Signal Processing (1986), IEEE Press, New York
19. D.J. Soudris, M.M. Dasigenis, A.T. Thanailakis, Designing RNS and QRNS adder based converters, 2000, in: IEEE International Symposium on Circuits and Systems: Emerging Technology for the 21st Century 1, 2000, pp. 20-23.
20. Stouraitis T. Efficient Convertors for residue and quadratic-residue number systems. IEE Proceedings, Part G: circuits, Devices and Systems 6 139 (1992) 626-634
21. Szabo N.S., and Tanaka R.J. Residue Arithmetic and its Applications to Computer Technology (1967), McGraw-Hill
22. Taylor F.J. Residue arithmetic: a tutorial with examples. Computer 17 5 (1984) 50-62
23. Vinod A.P., and Premkumar A.B. A memoryless reverse converter for the 4-moduli superset. Journal of Circuits, Systems and Computers 10 1-2 (2000) 85-99
24. Wang Y. Residue-to-binary converters based on new Chinese remainder theorems. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47 3 (2000) 197-205
25. Wang Y., Swamy M.N., and Ahmad M.O. Residue-to-binary number converters for three moduli sets. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46 2 (1999) 180-183
26. Wang Z., Jullien G.A., and Miller W.C. An efficient 3-modulus residue to binary converter. Proceedings of the 39th Midwest Symposium on Circuits and Systems, 18-21 August (1996), IEEE, Ames, IA, USA 1305-1308
27. Waser S., and Flynn M.J. Introduction to Arithmetic for Digital Systems Designers (1982), HRW, New York